Memory Array Access Lines With Oxide Layer for Current Spike Control
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Solution Overview
Problem
Memory cells in memory arrays experience damage due to current spikes caused by charge discharge through access lines, leading to degradation over time, especially near memory cells which have a low resistance path and far memory cells which require high drive currents due to high resistance.
Innovation Solution
A first metal layer is formed above vias and oxidized, with a second metal layer formed on top, creating a metal oxide layer that reduces current spikes and resistivity of access lines, thereby mitigating the difference in electrical distance between near and far memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If access lines are made with low resistance to reduce drive current requirements, then far memory cells can be accessed with lower power, but near memory cells experience severe current spikes due to the low resistance path
Solution Approach 1:
The access line is divided into segments with different resistance characteristics. A first portion (near the memory cell) has higher resistance to limit current spikes, while a second portion (far from the memory cell) has lower resistance to reduce drive current requirements. This is achieved by using different metal layers or material compositions in different spatial regions of the access line.
Solution Approach 2:
The access line is segmented into multiple portions with different electrical properties. The first portion uses a first metal layer with specific resistivity, while the second portion uses a second metal layer with different resistivity. This segmentation allows each portion to be optimized for its specific function: current limiting near the cell and power-efficient signal transmission farther away.
2Object-affected harmful factors
If access lines have high resistance to limit current spikes near memory cells, then near memory cells are protected from damage, but far memory cells require excessive drive currents
Solution Approach 1:
Different portions of the access line are assigned different resistance qualities based on their functional requirements. The first portion near the memory cell has higher resistance for protection, while the second portion extends to lower resistance for efficient signal transmission over distance, minimizing overall power consumption.
Solution Approach 2:
The access line is divided into functional segments: a first segment with higher resistance to protect near memory cells from current spikes, and a second segment with lower resistance to reduce the power required to drive signals to far memory cells. This segmented approach resolves the contradiction between local protection and global efficiency.
3Ease of manufacture
If uniform resistance is used throughout the access line, then manufacturing is simpler, but the electrical distance difference between near and far memory cells causes performance variability
Solution Approach 1:
The access line employs different material properties in different regions to achieve consistent performance across all memory cells. By adjusting the resistance characteristics locally in different portions of the access line, the patent compensates for the varying electrical distances, ensuring uniform memory cell performance despite positional differences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces current spikes, decreases power consumption, and optimizes drive currents, leading to improved memory cell durability and performance by reducing the relative differences in electrical distance between near and far memory cells.
Implementation Method 1
A first metal layer is formed above vias and oxidized, with a second metal layer formed on top, creating a metal oxide layer that reduces current spikes and resistivity of access lines
Data Source
AI summary
Methods, systems, and devices for reduced resistivity for access lines in a memory array are described. A first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. The first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. One or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.