Memory Access Management for Non-Volatile Storage Security

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Solution Overview

Problem

Existing memory access management techniques are inadequate in preventing unauthorized access to non-volatile memory devices, particularly during transit or when devices are lost/stolen, as they rely on time-consuming erase operations or physical destruction, which are not always feasible or environmentally friendly.

Innovation Solution

Implementing a memory access management component that detects specific events, such as power-up or remote 'kill switch' triggers, to disable or enable access to non-volatile memory sub-systems without requiring manual initiation or performing erase operations, thereby preventing unwanted access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If erase operations are performed to prevent unauthorized access to memory devices, then data security is improved, but the process becomes time-consuming and may not be feasible in all scenarios

Engineering Contradiction:
Improvedata securityVSAvoiderase operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by disabling memory access before unauthorized access can occur. The system proactively disables the memory interface or controller in response to detecting events such as removal from a host system, power-off conditions, or security threats, preventing unauthorized access without requiring time-consuming erase operations. This advance disabling ensures data security is maintained while avoiding the time loss associated with erasing data.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If physical destruction is performed to prevent unauthorized access, then data security is improved, but the device becomes unusable and the process is irreversible

Engineering Contradiction:
Improvedata securityVSAvoiddevice usability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent applies dynamics by implementing a reversible disablement mechanism rather than irreversible physical destruction. The memory access management component can dynamically switch between enabled and disabled states based on security conditions. When a security event is detected, access is disabled; when the security condition is resolved or a valid access request is received, access can be re-enabled. This dynamic approach maintains data security while preserving device usability, allowing the system to adapt to changing security conditions without permanent damage.

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If manual initiation is required for security measures, then control over security actions is improved, but the response time to prevent unauthorized access is delayed

Engineering Contradiction:
Improvecontrol over security actionsVSAvoidresponse time
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The patent applies self-service by implementing an automated security response system that detects security events and disables memory access without requiring manual initiation. The memory access management component continuously monitors for security-relevant events such as host system removal, power-off conditions, or authentication failures. Upon detecting such events, the system automatically disables the memory interface or controller, providing rapid response to security threats. This automated approach eliminates the delay associated with manual intervention while maintaining appropriate control through programmable security policies and event detection criteria.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20230063057A1Memory access managment
Publication Date: 2023.03.02 MICRON TECHNOLOGY INC
  • US20230063057A1 patent drawing
  • US20230063057A1 patent drawing
  • US20230063057A1 patent drawing

AI summary

A method includes detecting an occurrence of an event associated with a memory sub-system comprising blocks of non-volatile memory cells. The method further includes responsive to detecting the occurrence of the event, providing signaling to disable at least a portion of the memory sub-system, an interface coupled to the memory sub-system, or both.