Memory Access Optimization for Network Traffic Statistics
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Solution Overview
Problem
Existing network testing systems face inefficiencies in memory access latency, leading to delays in computing and reporting network traffic statistics due to the overhead of writing data to dynamic random access memory (DRAM), which affects the speed and accuracy of network performance analysis.
Innovation Solution
Implementing a pipelined memory access method where partial network traffic statistics are stored and accessed in a round-robin fashion across multiple memory banks, allowing concurrent reading and processing of data while writing updated statistics to another bank, thereby reducing memory latency and improving the speed of network traffic statistics computation and reporting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data is written to DRAM for network traffic statistics computation, then network performance analysis can be performed, but memory access latency increases causing delays in statistics computation and reporting
Solution Approach 1:
The memory system is divided into multiple independent memory banks (Bank 0, Bank 1, Bank 2, Bank 3) that can be accessed simultaneously. Statistics data is distributed across these banks, allowing parallel read operations to occur without waiting for sequential memory access, thereby reducing overall latency while maintaining data integrity for accurate network traffic statistics computation.
Solution Approach 2:
Memory banks are pre-configured with specific data types (Bank 0 for packet counts, Bank 1 for byte counts, Bank 2 for minimum latency, Bank 3 for maximum latency) before computation begins. This preliminary organization allows the statistics computation engine to directly access required data without additional lookup or data reorganization, reducing access time while ensuring accurate measurement of network traffic parameters.
2Productivity
If network traffic statistics are computed in real-time, then network performance analysis speed improves, but memory access overhead increases
Solution Approach 1:
By segmenting statistics data across multiple memory banks, the system enables parallel access to different data types simultaneously. This segmentation allows the computation engine to retrieve all necessary statistics (packet counts, byte counts, latency values) in parallel operations rather than sequential access, improving computation speed while distributing memory access load to reduce overall overhead.
Solution Approach 2:
The patent combines multiple statistics computation functions (packet counting, byte counting, minimum latency tracking, maximum latency tracking) into a single integrated memory access framework. By merging these functions and organizing their data in dedicated memory banks, the system achieves efficient bulk operations that improve overall computation productivity while reducing redundant memory access overhead through consolidated data structures.
Data Source
AI summary
A method and an apparatus for memory access optimization are disclosed. Data unit information may be accumulated for a plurality of data units. Partial network statistics for the plurality of data units may be read sequentially in round robin fashion from each of a plurality of memory banks of a memory. The partial networks statistics may be updated based on the plurality of data units. The updated partial network statistics may be written sequentially in round robin fashion to each of the plurality of memory banks.