Memory Access Node Segmentation for Reliability-Performance Trade-offs
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Solution Overview
Problem
Current information handling systems face performance trade-offs when using multiple memory controllers, where combining 64-bit controllers results in increased memory management reliability but decreased performance, and there is a need for efficient access to memory in multiple processor configurations.
Innovation Solution
A method and system that allow a multiple core processor to access memory through both grouped and ungrouped memory access nodes, enabling different data rate values and BIOS entries for each, allowing critical applications to prioritize reliability and non-critical applications to prioritize performance by selecting appropriate memory access nodes during runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple 64-bit memory controllers are combined into one 128-bit controller (ganged mode), then memory management reliability is improved, but data transfer performance deteriorates
Solution Approach 1:
The patent divides the memory controller resources into separate segments - some memory access nodes operate in ganged mode (combined controllers for reliability) while others operate in un-ganged mode (independent controllers for performance). This segmentation allows different applications to access different nodes based on their requirements, resolving the contradiction between reliability and performance.
Solution Approach 2:
The system dynamically assigns applications to different memory access node configurations based on their requirements. Critical applications are directed to ganged nodes for reliability, while non-critical applications use un-ganged nodes for performance. This dynamic allocation allows the system to adapt to different operational needs and resolve the reliability-performance tradeoff.
2Productivity
If multiple 64-bit memory controllers operate independently (un-ganged mode), then data transfer performance is improved, but memory management reliability deteriorates
Solution Approach 1:
The patent creates separate memory access pathways - un-ganged nodes for performance-critical operations and ganged nodes for reliability-critical operations. This segmentation allows the system to exploit the performance benefits of independent controllers without sacrificing the reliability benefits where needed.
Solution Approach 2:
Different regions of the memory subsystem are configured with different qualities - un-ganged nodes provide high-speed access for non-critical data, while ganged nodes provide high-reliability access for critical data. This local differentiation resolves the contradiction by providing the appropriate characteristic in the appropriate location.
3Device complexity
If a single memory controller configuration is used for all applications, then system simplicity is maintained, but adaptability to different application needs deteriorates
Solution Approach 1:
The memory subsystem is designed with multi-functional capability - it can operate in both ganged and un-ganged modes simultaneously, allowing different applications to access different nodes based on their requirements. This universality allows a single system to serve multiple purposes without requiring separate hardware configurations.
Solution Approach 2:
The system dynamically configures memory access based on application requirements rather than requiring static configuration. The operating system or memory management unit can direct different applications to different memory access nodes based on their criticality and performance needs, providing adaptability without increasing physical complexity.
Data Source
AI summary
A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation of the first memory access node to a first data rate value. The method can also include initiating operation of a second memory access node to a second data rate value. In one form, the second data rate value can be different from the first data rate value. The method can also include enabling a first application access to either the first memory access node or the second memory access node via an operating system enabled by the processor.