Memory Access Order Encoding in Block-Based Processors
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Solution Overview
Problem
Superscalar out-of-order microarchitectures face challenges with resource intensity, complexity, and inefficiency due to register renaming, dataflow analysis, and misspeculation recovery, limiting performance improvements in processor ISAs.
Innovation Solution
The implementation of a block-based processor using an EDGE ISA that executes instructions atomically within blocks, eliminating the need for complex features like register renaming and supporting high instruction-level parallelism, while utilizing a hybrid dataflow execution model to enhance performance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If superscalar out-of-order microarchitectures are used to improve processor performance, then instruction-level parallelism is enhanced, but device complexity and resource intensity increase due to register renaming, dataflow analysis, and misspeculation recovery
Solution Approach 1:
The processor architecture is segmented into fixed-size instruction blocks (e.g., 4 instructions per block) that are executed atomically. This segmentation eliminates the need for complex runtime register renaming and dataflow analysis by pre-organizing instructions into self-contained units with explicit dependency encoding, thereby reducing device complexity while maintaining parallelism capabilities
Solution Approach 2:
Data dependencies and memory access orders are predetermined and encoded in the instruction block structure during compilation. The compiler performs preliminary analysis to assign load-store identifiers (LSIDs) that encode execution order, eliminating the need for complex runtime speculation and recovery mechanisms, thus reducing processor complexity while preserving performance
2Productivity
If complex features like register renaming and dataflow analysis are implemented to support out-of-order execution, then instruction-level parallelism is improved, but power consumption increases
Solution Approach 1:
The complex features of register renaming, dataflow analysis, and misspeculation recovery are extracted and eliminated from the processor microarchitecture. Instead, simpler in-order execution within fixed instruction blocks is used, with parallelism achieved through block-level out-of-order execution and explicit dependency encoding, significantly reducing power consumption while maintaining instruction-level parallelism
Solution Approach 2:
The architecture changes from dynamic out-of-order execution with complex hardware to fixed-block atomic execution with simplified hardware. By changing the execution model parameter from dynamic speculation to static block-based execution, power consumption is reduced while instruction-level parallelism is preserved through compiler-optimized block scheduling
3Device complexity
If memory access instructions are executed without explicit ordering encoding, then processor simplicity is maintained, but memory access hazards occur reducing performance
Solution Approach 1:
Load-store identifiers (LSIDs) serve as an intermediary encoding mechanism that explicitly specifies memory access instruction order within instruction blocks. This intermediary encoding allows the simple in-order execution hardware to correctly handle memory dependencies without complex hazard detection logic, maintaining processor simplicity while eliminating performance-reducing memory access hazards
Data Source
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AI summary
Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.