Memory Access Pattern Monitor for Shared Cache Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional eviction procedures in multi-core data processing devices are inefficient due to shared memory hierarchy levels, leading to suboptimal memory access management across different processor cores.
Innovation Solution
A memory access pattern monitor predicts access patterns for each thread and adjusts resource allocation in the shared cache, prioritizing cache line replacement based on temporal and spatial locality, ensuring efficient execution by optimizing memory access for threads with higher temporal locality and minimizing performance degradation for those with higher spatial locality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional eviction procedures are used in multi-core data processing devices, then memory management is simplified, but memory access efficiency deteriorates due to shared memory hierarchy levels
Solution Approach 1:
The patent segments the shared cache into multiple ways, with each way dedicated to a specific processor core. This segmentation allows each core to have its own eviction policy and access patterns tracked independently, resolving the conflict between simplified management and efficient access by providing structured organization of the shared resource.
Solution Approach 2:
The patent implements preliminary action by predicting memory access patterns before actual access occurs. The system tracks historical access patterns and uses this information to proactively manage cache line eviction and allocation, allowing the system to prepare optimal cache configurations in advance rather than reacting to misses after they occur.
2Productivity
If cache lines are evicted to make room for recently accessed information, then memory hierarchy efficiency is improved, but performance of threads with spatial locality deteriorates
Solution Approach 1:
The patent implements feedback mechanisms that continuously monitor access patterns of multiple threads and use this information to make intelligent eviction decisions. The system feedback loop tracks which threads exhibit temporal versus spatial locality patterns and adjusts cache line retention accordingly, ensuring that eviction actions benefit overall system performance while minimizing impact on individual thread performance.
Solution Approach 2:
The patent applies local quality by treating different cache lines differently based on their specific access patterns. Rather than applying a uniform eviction policy, the system identifies which cache lines are associated with threads exhibiting temporal locality versus spatial locality and applies differentiated retention strategies, keeping lines with temporal locality longer while being more aggressive in evicting lines with spatial locality patterns.
3Quantity of substance
If shared cache levels are used across multiple cores, then resource utilization is improved, but access pattern interference between threads increases
Solution Approach 1:
The patent segments the shared cache into multiple independent ways, each associated with a specific processor core. This segmentation reduces access pattern interference by providing isolated access paths for different cores while maintaining overall shared resource utilization. Each core's access patterns are tracked and managed independently within its dedicated way, preventing interference from other cores' access patterns.
Solution Approach 2:
The patent implements dynamic cache management that adapts to changing access patterns in real-time. The system continuously monitors which threads are active and their access characteristics, dynamically adjusting which cache lines are retained or evicted based on current workload conditions. This dynamic approach allows the cache to optimize for current access patterns while maintaining flexibility to adapt as workloads change.
Data Source
AI summary
For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.