Memory Access Processor for Reconfigurable Computing
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Solution Overview
Problem
Conventional processor-memory architectures face inefficiencies due to power-hungry mechanisms that waste memory bandwidth and power, particularly in handling cache lines and prefetching data, which are not fully utilized, leading to increased power consumption and reduced processing speed.
Innovation Solution
A computing system with a reconfigurable computing device and a programmable memory access processor that performs parallel processing, optimized for address generation, address mapping, and access scheduling, allowing for efficient data transfer and configuration, thereby minimizing intermediate buffering and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory access mechanisms (cache lines, prefetching) are used to reduce access latency, then processing speed is improved, but power consumption increases and memory bandwidth is wasted
Solution Approach 1:
The patent segments the data transfer process by implementing fine-grained data transfer at the byte level rather than transferring complete cache lines. The memory system is divided into multiple independent transfer operations, where only the specific bytes needed by the processor are transferred, eliminating the waste of transferring unused data and reducing power consumption proportionally.
Solution Approach 2:
The patent applies partial action by transferring only the necessary portion of data (specific bytes) rather than the complete data unit (cache line). The processor requests specific bytes, and the memory system transfers only those bytes, avoiding the excessive transfer of unnecessary data that would consume additional power and bandwidth.
2Speed
If complete cache lines are retrieved from memory system, then access latency is reduced, but memory bandwidth is wasted due to unused bytes
Solution Approach 1:
The patent segments the cache line transfer into individual byte-level transfers. Instead of retrieving the entire cache line, the memory system identifies and transfers only the specific bytes requested by the processor. This segmentation allows precise control over memory bandwidth usage, ensuring that only necessary data is transferred.
Solution Approach 2:
The patent applies local quality by treating each byte within the cache line differently based on whether it is needed or not. The memory system identifies the specific bytes that are required and gives them priority for transfer, while leaving unused bytes untransferred. This localized approach optimizes bandwidth utilization by focusing resources only on necessary data.
3Speed
If prefetching mechanisms are used to reduce average access latency, then processing speed is improved, but power is wasted on unneeded data accesses and operations
Solution Approach 1:
The patent applies preliminary action by having the processor explicitly request specific bytes it needs in advance, allowing the memory system to prepare and transfer only those specific bytes. This prevents the waste of prefetching unnecessary data, as the processor's explicit requests guide the memory system to pre-fetch only the required data, eliminating energy waste on unneeded prefetching operations.
Data Source
AI summary
A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.