Memory Access Randomization for Faulty Memory Reliability

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Solution Overview

Problem

Current technologies face challenges in managing faulty memories and ensuring quality in integrated circuits due to deterministic manufacturing variations, leading to high discard rates and increased costs from stringent testing and design margins, as existing fault models do not accurately reflect real-world manufacturing defects and variations.

Innovation Solution

A method is introduced to restore an ergodic fault behavior in faulty memories by using randomization logic to create a time-varying behavior for logical memory spaces, converting deterministic faults into random faults, and randomizing memory access operations to achieve stable time-average quality across a population of dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If stringent testing and design margins are applied to ensure quality in integrated circuits, then reliability is improved, but discard rates increase and costs increase

Engineering Contradiction:

ImprovequalityVSAvoiddiscard rates

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent changes the fundamental parameter of fault behavior from deterministic to random through the introduction of randomization logic. This transforms how faults manifest in the system, allowing faulty memories to exhibit ergodic behavior that can be statistically managed rather than deterministically failed, thereby reducing discard rates while maintaining quality

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces randomization logic as an intermediary component between the control logic and the faulty memory. This intermediary randomizes memory access operations and addresses, converting deterministic fault patterns into random ones, which enables the system to tolerate faults without requiring stringent testing and design margins

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If deterministic fault models are used for manufacturing, then manufacturing precision is maintained, but quality varies across dies and discard rates increase

Engineering Contradiction:

Improvemanufacturing variationsVSAvoidquality consistency

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent makes the fault behavior dynamic by introducing time-varying randomization. Instead of static deterministic faults, the system now exhibits dynamic random fault patterns that change over time, allowing quality to be consistent across dies through statistical ergodic behavior rather than uniform manufacturing precision

Inventive Principle:

Principle #15Dynamics

3Reliability

If reliable memories are used, then quality is maintained, but energy consumption increases and area efficiency decreases

Engineering Contradiction:

ImprovequalityVSAvoidenergy efficiency

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent converts the harmful effect of memory faults into a beneficial outcome by introducing randomization logic. Instead of avoiding faults entirely (which would require reliable memories with higher energy consumption), the system embraces faulty memories and uses randomization to make their behavior predictable in a statistical sense, thereby achieving quality maintenance with lower energy consumption and improved area efficiency

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12057858B2Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Publication Date: 2024.08.06 ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

AI summary

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomizing the memory access operation with a randomization logic to access data from a physical memory space based on the logical memory space, the randomization logic providing time varying behavior for accessing the physical memory space.