Memory Access System for NAND Flash Read Disturb Mitigation
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Solution Overview
Problem
NAND flash memories experience unintended data rewriting due to repeated read operations, known as the 'read disturb phenomenon', which existing solutions cannot effectively address without relying on specific cell configurations.
Innovation Solution
A memory access system that includes a load count memory part to track read access loads, an error detection part to identify errors, and an error correction part to correct errors in both selected and unselected cells, thereby reducing the read disturb phenomenon without depending on cell configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If repeated read operations are performed on selected cells, then data can be accessed continuously, but unselected cells experience threshold voltage shifts causing unintended data rewriting
Solution Approach 1:
The patent applies preliminary action by performing error detection and correction on unselected cells before they actually suffer data corruption. The system proactively identifies cells at risk of read disturb errors and corrects them in advance, preventing the threshold voltage shifts from causing unintended data rewriting. This is achieved by monitoring read counts and applying corrective operations to unselected cells before their data integrity is compromised.
2Reliability
If error detection and correction are performed on all memory areas, then read disturb phenomenon is reduced, but system complexity increases
Solution Approach 1:
The patent applies local quality by performing error detection and correction selectively on specific memory areas rather than uniformly across the entire memory. The system identifies unselected cells that are susceptible to read disturb effects and applies corrective operations only to those specific locations. This localized approach reduces the overall system complexity compared to comprehensive error correction while still protecting against read disturb phenomenon in the most vulnerable areas.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a memory management unit that coordinates between read operations and error correction operations. This intermediary layer monitors read access patterns, identifies cells at risk, and triggers appropriate correction operations. By inserting this intermediary control layer, the system manages the complexity of error detection and correction without requiring fundamental changes to the underlying memory architecture.
3Reliability
If conventional error correction methods are used, then they work for specific cell configurations, but they cannot be applied to other memory types
Solution Approach 1:
The patent applies universality by designing an error detection and correction system that can operate across different memory types and cell configurations. The memory management unit implements a standardized interface and control logic that adapts to various memory architectures, including NAND flash and other non-volatile memories. This universal approach allows the same error correction mechanism to protect against read disturb phenomenon regardless of the specific memory technology being used, enhancing both reliability and adaptability.
Data Source
AI summary
When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.