Memory Access Reordering for Video Transform Throughput
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Solution Overview
Problem
Conventional video compression methods face inefficiencies in accessing multiple contiguous data points in memory, particularly when dealing with different transform block sizes and types, as they often require sequential access rather than parallel access, limiting memory throughput.
Innovation Solution
The implementation of a system with multiple memories and a circuit configuration that allows for parallel access of data points across different memories, enabling the transfer of 8 or 16 data points per clock cycle, regardless of transform block size or type, by reordering memory access to access rectangular regions of data points efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential memory access is used for transform blocks, then memory access order is simple, but memory throughput is limited and processing speed is reduced
Solution Approach 1:
The transform block is divided into multiple segments that can be accessed in parallel from different memories. The memory access is segmented into multiple independent read cycles, each accessing a different portion of the transform block simultaneously, thereby increasing overall memory throughput without requiring complex sequential ordering logic.
Solution Approach 2:
The patent introduces a new dimension to memory access by organizing data in a two-dimensional layout and accessing it along different dimensions (rows vs. columns). This allows the same transform block to be accessed in multiple orders (horizontal vs. vertical scanning) without changing the underlying data storage, resolving the contradiction between access flexibility and complexity.
2Adaptability or versatility
If hardware is designed to handle different transform sizes, then adaptability is improved, but hardware complexity increases
Solution Approach 1:
The memory access hardware is designed with universal interfaces and control logic that can handle multiple transform sizes (4×4, 8×8, 16×16) and transform types (frame, field) through the same basic architecture. By using parameterized address generation and flexible memory organization, the hardware achieves multi-functionality without requiring separate dedicated circuits for each transform size.
Solution Approach 2:
The patent uses parameter changes to adapt the memory access pattern to different transform sizes. By modifying address generation parameters, block size indicators, and memory address offsets based on the detected transform type, the same hardware structure can efficiently access data for various transform configurations without structural changes.
3Reliability
If data points are accessed in different orders based on transform type, then transform accuracy is maintained, but access time varies
Solution Approach 1:
The patent applies preliminary action by pre-organizing data in memory according to the expected transform type and size before the actual transform operation. Memory addresses and data layouts are prepared in advance based on macroblock characteristics, allowing the transform engine to access data in the optimal order without real-time decision delays, thus maintaining both accuracy and consistent access time.
Data Source
AI summary
An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.