Memory Access Scheduler for Bank Pre-Opening

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Solution Overview

Problem

In multi-bank memory systems, existing technologies face inefficiencies in managing memory access times and power consumption due to the need to constantly open and close banks and bank pages, leading to overhead and suboptimal bus utilization.

Innovation Solution

A memory access scheduler component predicts access patterns and pre-opens banks and bank pages before they are needed, reducing overhead and improving bus usage by issuing activation requests ahead of time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If banks are opened and closed on demand for each memory access, then memory access flexibility is improved, but overhead and access time increase

Engineering Contradiction:
Improvememory access flexibilityVSAvoidmemory access time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The memory controller predicts future memory access patterns and pre-opens bank pages before they are actually needed. By analyzing historical access patterns, the controller proactively activates banks in advance, eliminating the latency that would otherwise occur when banks need to be opened on-demand for each access operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts bank management strategies based on observed access patterns. The memory controller continuously monitors and adapts its predictions, switching between different bank opening strategies based on the specific access pattern being exhibited, thereby optimizing performance for different workloads.

Inventive Principle:
Principle #15Dynamics

2Speed

If banks are frequently opened and closed, then memory access responsiveness is improved, but power consumption increases

Engineering Contradiction:
Improvememory access responsivenessVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

By pre-opening banks based on predicted access patterns, the system avoids the need to frequently open and close banks in response to each access request. This reduces the number of bank state transitions, thereby lowering power consumption while maintaining responsive access times.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory controller maintains banks in an active state longer by predicting future accesses, thereby reducing the frequency of bank opening/closing operations. This continuous utilization strategy reduces the overhead associated with repeated bank activation, lowering overall power consumption.

Inventive Principle:
Principle #20Continuity of useful action

3Loss of time

If memory accesses are processed immediately upon request, then response time is improved, but bus utilization decreases

Engineering Contradiction:
Improveresponse timeVSAvoidbus utilization
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The memory controller issues bank activation requests in advance based on predicted access patterns, allowing bus operations to be better scheduled and utilized. By proactively managing bank states, the controller can batch operations and improve bus utilization without compromising the timing of actual data accesses.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9336164B2Scheduling memory banks based on memory access patterns
Publication Date: 2016.05.10 AMPERE COMPUTING LLC
  • US9336164B2 patent drawing
  • US9336164B2 patent drawing
  • US9336164B2 patent drawing

AI summary

Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory array. Accordingly, memory access overhead is reduced.