Hierarchical Memory Access Scheduler for DRAM Bandwidth
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Solution Overview
Problem
Existing memory controllers for DRAMs face challenges such as long latency, constraints on random accesses, and inefficient bandwidth utilization, leading to potential logical errors and suboptimal memory bus utilization due to unregulated sharing of read and write requests.
Innovation Solution
An access scheduler with hierarchical arbitration levels and timer-controlled masking ensures that DRAM accesses adhere to bank constraints, prioritizes requests, and dynamically allocates bandwidth between read and write operations, preventing logical errors and optimizing memory bus utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read and write accesses are reordered to maximize bandwidth utilization, then memory interface utilization is improved, but logical errors may occur due to reading before writing
Solution Approach 1:
The patent segments the memory access arbitration into multiple hierarchical levels: a first level arbiter handles basic access selection, while a second level arbiter handles reordering decisions. This segmentation allows the system to separately manage the constraints of logical correctness at the first level and the optimization of bandwidth utilization at the second level, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent implements preliminary action by having the first level arbiter establish and maintain the correct logical ordering of read and write accesses before the second level arbiter attempts to reorder accesses for bandwidth optimization. By pre-establishing the logical correctness constraints, the system can safely optimize bandwidth without violating data integrity requirements.
2Productivity
If multiple row activations are engaged concurrently within a time window, then bandwidth is improved, but the rolling time frame constraint tFAW is violated
Solution Approach 1:
The patent employs feedback mechanisms where the memory controller monitors the timing of row activations and adjusts subsequent access patterns to ensure compliance with the tFAW constraint. The system tracks the number of row activations within rolling time frames and provides feedback to the arbitration logic to prevent constraint violations while maximizing bandwidth utilization.
3Device complexity
If unregulated sharing of read and write requests is implemented, then device complexity is reduced, but memory bus stalls occur due to inefficient bandwidth utilization
Solution Approach 1:
The patent segments the arbitration function into two distinct levels: a first level arbiter that handles basic access request selection with relatively simple logic, and a second level arbiter that handles sophisticated reordering for bandwidth optimization. This segmentation allows the system to achieve high memory bus utilization through intelligent reordering while keeping each individual arbiter unit relatively simple, resolving the contradiction between device complexity and productivity.
Data Source
AI summary
Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation.