Memory Access Circuit With Selective Buffers for Low-Voltage Read Range
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Solution Overview
Problem
The decreasing reference voltage in integrated circuit devices affects the operation of memory elements, making it challenging to maintain read and write operations, particularly due to reduced slew rates and read voltage ranges.
Innovation Solution
The implementation of a circuit with selectively disabled line driver buffers and a unity gain buffer as a global supply, dynamically switching between NMOS and PMOS differential pairs based on read or write operations to extend the read range and improve operational margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If reference voltage is decreased to reduce power consumption, then power consumption is reduced, but read range and operational reliability of memory elements deteriorate
Solution Approach 1:
The address space is segmented into first and second portions, with corresponding first and second plurality of memory elements. Line driver buffers are selectively enabled or disabled based on which address portion is being accessed. This segmentation allows the circuit to operate reliably at lower reference voltages by limiting the active memory portion, thereby maintaining read range while reducing overall power consumption.
Solution Approach 2:
The circuit dynamically switches between PMOS and NMOS differential pairs based on operational mode (read or write). During read operations, PMOS differential pairs are used to extend read range, while during write operations, NMOS differential pairs are used. This dynamic switching allows the circuit to maintain optimal performance across different operations while operating at reduced reference voltages.
2Area of stationary object
If reference voltage is decreased to improve integration density, then integration density is improved, but slew rate and signal integrity deteriorate
Solution Approach 1:
The circuit changes operational parameters by selectively enabling or disabling line driver buffers based on the address portion being accessed. This parameter change allows the circuit to maintain adequate slew rates for active memory portions while keeping other portions in a low-power state, effectively maintaining signal integrity at reduced reference voltages without compromising integration density.
3Reliability
If all line driver buffers are always enabled to maintain read range, then read range is maintained, but power consumption and frame loading increase
Solution Approach 1:
The address space is segmented into first and second portions, with corresponding first and second plurality of memory elements. Line driver buffers are selectively enabled or disabled based on which address portion is being accessed. This segmentation allows the circuit to maintain read range for active memory portions while keeping other portions in a low-power state, thereby reducing overall power consumption and frame loading.
Data Source
AI summary
A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.