Memory Access Status Signaling to Prevent Host Resets

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Solution Overview

Problem

Current memory systems face performance degradation due to unnecessary reset operations when delays occur, as the host system assumes failure without clear status updates from the memory system, leading to inappropriate responses and potential deadlocks.

Innovation Solution

Implementing access operation status signaling between the host system and the memory system to indicate ongoing error recovery or media management operations, allowing the host system to make informed decisions about continuing or aborting these processes, thus avoiding unnecessary resets and improving system flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the host system assumes failure when access operation duration exceeds a threshold, then the system can quickly respond to potential failures, but unnecessary reset operations are triggered causing performance degradation

Engineering Contradiction:
Improvefailure detection accuracyVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory system provides feedback signals to the host system indicating whether an access operation is stuck or merely delayed. This feedback mechanism allows the host to distinguish between actual failures and temporary delays, preventing unnecessary reset operations while maintaining reliable failure detection.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The memory system performs preliminary actions by proactively signaling its status before the host's timeout threshold is exceeded. By providing early status updates about ongoing operations (error recovery, media management), the memory system prevents the host from incorrectly assuming failure and initiating unnecessary resets.

Inventive Principle:
Principle #10Preliminary action

2Loss of information

If the host system waits for memory operation completion, then accurate status information is obtained, but system latency increases and responsiveness deteriorates

Engineering Contradiction:
Improvestatus information accuracyVSAvoidsystem latency
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The memory system provides periodic status updates during access operations through interrupt signals or status registers. This periodic feedback allows the host system to check operation status at intervals rather than waiting for completion, reducing latency while maintaining accurate status information.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The memory system implements continuous feedback mechanisms that provide real-time status information to the host system. Through status registers, interrupt signals, or direct memory access (DMA) notifications, the host can poll or receive asynchronous updates about operation progress without blocking, thereby reducing latency while maintaining information accuracy.

Inventive Principle:
Principle #23Feedback

3Reliability

If the memory system performs error recovery operations, then data integrity is improved, but access operation duration increases causing host system timeouts

Engineering Contradiction:
Improvedata integrityVSAvoidaccess operation duration
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The memory system performs preliminary actions by signaling to the host before initiating error recovery operations. This advance notification allows the host to extend its timeout threshold or enter a waiting state, preventing false timeout assumptions while maintaining data integrity through necessary error recovery processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory system implements feedback mechanisms that inform the host about ongoing error recovery operations. Through status registers or interrupt signals, the memory system communicates that an access operation is stuck due to error recovery, allowing the host to differentiate between temporary delays and actual failures, thereby managing timeout behavior appropriately.

Inventive Principle:
Principle #23Feedback

4Reliability

If the host system initiates reset operations on timeout, then potential failures are addressed, but system deadlocks occur when memory is actively performing operations

Engineering Contradiction:
Improvefailure responseVSAvoidsystem flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory system provides feedback signals that indicate whether a timeout is due to an actual failure or an ongoing operation (error recovery, media management). This feedback enables the host to adapt its response - initiating reset only for actual failures while allowing ongoing operations to complete, thereby preventing deadlocks and maintaining system flexibility.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system implements dynamic timeout management where the timeout threshold or response behavior changes based on memory system status. When the memory signals ongoing operations, the host dynamically adjusts by extending timeouts or entering wait states. When actual failures are detected, the host returns to standard timeout behavior, creating a flexible and adaptive failure response mechanism.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12124322B2Access operation status signaling for memory systems
Publication Date: 2024.10.22 MICRON TECHNOLOGY INC
  • US12124322B2 patent drawing
  • US12124322B2 patent drawing
  • US12124322B2 patent drawing

AI summary

Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.