Memory Access System with Structure Access Circuit for Address Translation
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Solution Overview
Problem
Conventional memory access systems face challenges in extending addressing capability, leading to increased computing overhead and power consumption due to the need for complex computations to determine physical addresses, which affects processor performance.
Innovation Solution
A memory access system that abstracts memory into data structures, using a structure access circuit to generate physical addresses based on configuration information, allowing processors to access memory through structure elements or sub-elements instead of physical addresses, thereby reducing computational overhead and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the processor determines physical addresses using base address and offset computations, then the addressing capability is extended beyond the processor's native capability, but the computing overhead and power consumption increase significantly
Solution Approach 1:
The patent introduces a memory management unit (MMU) as an intermediary component between the processor and memory. The MMU handles address translation by combining base addresses and offsets to generate physical addresses, thereby extending the processor's addressing capability without requiring the processor itself to perform these computations. This mediator approach resolves the contradiction by enabling extended addressing while keeping the processor's power consumption low.
Solution Approach 2:
The address space is segmented into base addresses (stored in register files) and offsets (provided by the processor). This segmentation allows the system to extend addressing capability by combining these two components, while the MMU handles the combination process separately from the processor, reducing the processor's computational burden and power consumption.
2Adaptability or versatility
If the processor performs address determination computations, then the addressing capability is extended, but the number of processing cycles increases, affecting processor performance
Solution Approach 1:
The MMU acts as an intermediary that handles address translation operations separately from the processor's main execution pipeline. By offloading address determination computations to the MMU, the processor can focus on executing instruction logic without being burdened by address calculation overhead, thus maintaining high processor performance while achieving extended addressing capability.
Solution Approach 2:
Base addresses are pre-loaded into register files of the MMU before address translation is needed. This preliminary action allows the MMU to quickly combine pre-stored base addresses with offsets during address translation, reducing the number of processing cycles required and improving overall processor performance.
3Adaptability or versatility
If the addressing capability is extended through base address and offset computations, then memory access beyond native capability is enabled, but the computing overhead on the processor increases
Solution Approach 1:
The MMU serves as a specialized intermediary device that handles the complexity of address translation. It contains register files for storing base addresses and logic for combining base addresses with offsets. This separates the computing overhead from the processor, enabling extended addressing capability while keeping the processor's computing overhead low.
Solution Approach 2:
The MMU maintains copies of base addresses in its register files, allowing quick access and combination with offsets during address translation. This copying mechanism enables efficient address generation without requiring the processor to repeatedly access or compute base addresses, reducing computing overhead while maintaining extended addressing capability.
Data Source
AI summary
A memory access system includes a memory that is abstracted into data structures. The memory access system further includes a processor that generates an access request for accessing the abstracted memory by way of a structure access circuit of the memory access system. As the memory is abstracted into the data structures and the processor accesses the abstracted memory using the data structures, an addressing capability of the processor is extended. Further, the computing overhead of the processor is reduced, as the processor performs various memory operations by accessing the memory by way of the structure access circuit.