Memory Access Throttling with Timers and Credits

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Solution Overview

Problem

Memory systems face challenges with increasing costs, complexity, and reduced device life due to non-linear performance and capacity improvements, necessitating improved performance management to meet market expectations and environmental sustainability.

Innovation Solution

Implementing timers and credit-based approaches to manage memory system performance by delaying operations until target data rates are met, using techniques such as throttling and credit accumulation to control access commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory system operates at high data rates continuously, then productivity is improved, but device lifetime deteriorates

Engineering Contradiction:
Improvedata rateVSAvoiddevice lifetime
Core Design Contradiction:
ProductivityVSDuration of action of stationary object

Solution Approach 1:

The patent implements periodic action by using timers to introduce deliberate pauses between memory access operations. The timer mechanism allows the memory system to alternate between high-speed operation periods and rest periods, preventing continuous high-rate operation that would degrade device lifetime while still achieving high productivity during active periods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies dynamics by making the memory system's operational characteristics adjustable rather than fixed. Through configurable timer parameters and performance thresholds, the system can dynamically adapt its data rate and operation frequency based on workload conditions, allowing optimization between productivity and device lifetime depending on operational requirements.

Inventive Principle:
Principle #15Dynamics

2Reliability

If memory system implements performance management features, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveperformance controlVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling the memory system to autonomously manage its own performance through integrated timer circuits and control logic. The system automatically monitors its operational state, evaluates performance thresholds, and adjusts its operation without requiring external intervention, thereby improving reliability while minimizing the complexity increase that would result from external management systems.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent applies feedback mechanisms where the memory system continuously monitors its operational parameters (such as data rate and timer expiration) and adjusts its behavior accordingly. This feedback loop enables automatic performance management, improving reliability through self-regulation while keeping the added complexity contained within the system's own control architecture.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250355566A1Memory performance management
Publication Date: 2025.11.20 MICRON TECHNOLOGY INC
  • US20250355566A1 patent drawing
  • US20250355566A1 patent drawing
  • US20250355566A1 patent drawing

AI summary

Methods, systems, and devices for memory performance management are described. A memory system may limit performance, such as in accordance with a target data rate for the memory system. For example, the memory system may implement one or more timers. In response to receiving an access command, the memory system may initiate a timer, and may delay (e.g., suppress) performing other access commands until expiration of the timer. Additionally, or alternatively, the memory system may implement a credit-based approach to manage performance. For example, the memory system may periodically issue credits, such as by incrementing a counter. The memory system may consume credits to perform access commands. If the memory system receives a command to perform an access operation and does not have sufficient credits to perform the operation, the memory system may delay the operation, for example until sufficient credits are accrued.