Memory Access Unit Concurrent Multi-Dimensional Array Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies when processing multi-dimensional data, as they often require reordering samples to access data in different dimensions, leading to increased computation overhead and memory requirements, particularly in applications like image processing and radar signal processing.
Innovation Solution
A memory access unit with k address calculators and sample collectors that allow concurrent access to k*m memories by generating addresses and memory selects based on d-dimensional arrays, enabling data transfer without reordering, thus optimizing bus utilization and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If samples are re-ordered between processing steps to access data in different dimensions, then data accessibility in multiple dimensions is improved, but computation overhead and memory requirements increase
Solution Approach 1:
The memory system is segmented into k*m separate memory modules arranged in a k-by-m array, where each memory module stores a portion of the d-dimensional data array. This segmentation allows different memory modules to be accessed concurrently through different data buses, enabling multi-dimensional data access without requiring sample re-ordering operations, thus reducing computation overhead while maintaining data accessibility.
Solution Approach 2:
The patent introduces a new dimensional organization of memory modules (k-by-m array) that maps the d-dimensional data array in a way that enables orthogonal access patterns. By organizing memories in multiple dimensions and using address calculators to generate addresses in each dimension, the system allows simultaneous access along different dimensions without reordering samples, resolving the contradiction between adaptability and device complexity.
2Adaptability or versatility
If memory allows data to be read out in orthogonal dimensions, then data access flexibility is improved, but memory complexity increases
Solution Approach 1:
The memory system is divided into k*m independent memory modules arranged in a k-by-m array, with each module accessible through dedicated data buses. This segmentation enables orthogonal dimension access by directing different dimensional accesses to different memory modules, providing data access flexibility while keeping individual memory module complexity manageable.
Solution Approach 2:
Address calculators and sample collectors act as intermediary components that translate logical addresses into physical memory addresses and generate appropriate memory select signals. These intermediaries enable orthogonal dimension access without requiring the memory modules themselves to be complex, as the address translation and selection logic is handled by the intermediary components.
3Productivity
If concurrent access to multiple memories is enabled, then data transfer rate is improved, but control complexity increases
Solution Approach 1:
The memory system is segmented into k*m modules that can be accessed concurrently through different data buses, enabling parallel data transfer operations. Each memory module can be accessed independently, allowing simultaneous read/write operations across multiple dimensions, which increases data transfer rate while the modular structure keeps control complexity manageable through standardized access patterns.
Solution Approach 2:
Address calculators pre-calculate the addresses in each dimension and generate memory select signals before the actual data transfer occurs. This preliminary action of address generation and memory selection enables concurrent access to multiple memory modules without conflict, as the target memories are identified and selected in advance, reducing control complexity during the actual data transfer phase.
Data Source
AI summary
A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m≥1, and k*m memories, where k≥2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories. Each sample collector is configured to calculate a respective memory select in dependence upon the address in each of the d dimensions such that each sample collector selects a different one of the k*m memories so as to allow the sample collectors to access k of the k*m memories concurrently. A memory controller may comprise m memory access units for handling transfers of samples in a d-dimensional array between m data buses and k*m memories. An integrated circuit (IC) comprising a memory access unit, and a motor vehicle comprising a computing device having a memory access unit are also disclosed.