Memory Activate Signaling Using Preceding Command V Bits
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Solution Overview
Problem
Existing memory devices face challenges in transmitting additional activate information without increasing command/address (CA) bus pins, clock cycles, or circuit area, which affects performance and flexibility in activating memory cells.
Innovation Solution
Utilize unused valid (V) bits in preceding commands to transmit additional activate information to memory devices, allowing flexible page size activation without impacting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If additional activate information is transmitted using existing CA bus pins, then transmission capability is improved, but command cycle time increases
Solution Approach 1:
The patent applies preliminary action by transmitting portions of the activate address in advance during the read command phase. Specifically, the read command transmits first and second portions of the activate address on its command/address bus, which are then combined later with a third portion to form the complete activate address. This allows the activate information to be prepared and transmitted beforehand, reducing the time required when the actual activate operation needs to occur.
2Loss of information
If additional activate information is transmitted by increasing clock cycles, then information transmission is improved, but system performance deteriorates
Solution Approach 1:
The patent applies merging by combining multiple pieces of information into a single integrated transmission sequence. The read command is merged to carry both its primary function (data read) and the additional function of transmitting activate address portions. Similarly, the activate command is merged to receive and combine three separate address portions (first, second, and third portions) into a complete activate address, all within a single clock cycle operation.
3Adaptability or versatility
If dynamic page size activation is provided, then flexibility is improved, but additional activate information requirements increase
Solution Approach 1:
The patent applies universality by designing the command/address bus to serve multiple functions. The same bus infrastructure that normally handles standard read, write, and activate commands is enhanced to also carry dynamic page size activation information and additional activate address portions. This multi-functional approach allows the system to support both fixed and dynamic page sizes without requiring separate dedicated communication channels or significantly increasing overall system complexity.
Data Source
AI summary
A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.