Memory Activation Timing Management for Wear Prevention
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Solution Overview
Problem
Memory cells in volatile memory devices experience data corruption and premature wear-out due to 'continuous open page' (COP) and 'continuous closed page' (CCP) wear-out mechanisms, which occur from repeated activations in the same logic state without sufficient wait time.
Innovation Solution
Implementing memory activation timing management by imparting a delay for a third time period after pre-charging memory cells, especially when they are recently activated, to prevent COP and CCP wear-out mechanisms, while avoiding delays when the memory cells are not recently activated to maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are repeatedly activated in the same logic state without sufficient wait time, then memory access speed is improved, but data corruption and premature wear-out occur
Solution Approach 1:
The patent implements dynamic timing management by detecting whether a memory row has been recently activated and conditionally adjusting the wait time accordingly. When a row is recently activated, a longer third time period is imposed to prevent COP/CCP wear-out; when not recently activated, the standard timing is used to maintain performance. This dynamic adaptation resolves the contradiction between speed and reliability.
Solution Approach 2:
The patent changes the time period parameter based on the activation history of memory rows. By monitoring whether a row was activated within a recent time window and conditionally extending the third time period, the system adjusts timing parameters to prevent data corruption while maintaining optimal performance for non-recent activations.
2Reliability
If a delay is imposed after pre-charging memory cells, then memory cell wear-out is prevented, but memory access performance deteriorates
Solution Approach 1:
The patent applies the delay locally and selectively only to recently activated memory rows that are subject to COP/CCP wear-out mechanisms, rather than imposing a universal delay on all memory operations. This localized approach protects vulnerable memory cells while maintaining high performance for memory rows that do not require protection.
Solution Approach 2:
The system dynamically determines whether to impose the delay based on real-time detection of recent activation history. This conditional timing adjustment ensures that delays are applied only when necessary for reliability, thereby minimizing the impact on overall memory access performance.
3Productivity
If continuous repeated activations occur on the same memory row, then memory bandwidth utilization is improved, but charge leakage and data loss increase
Solution Approach 1:
The patent applies preliminary anti-action by detecting recent activations and proactively imposing a longer third time period before subsequent activations. This preventive measure counteracts the charge leakage effect by ensuring sufficient wait time accumulates before the memory row is activated again, thereby preventing data corruption before it occurs.
Data Source
AI summary
Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.