Memory Activation Timing Management for Wear-Out Prevention

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Solution Overview

Problem

Memory cells in volatile memory devices experience data corruption and premature wear-out due to continuous repeated access, leading to 'continuous open page' (COP) and 'continuous closed page' (CCP) wear-out mechanisms, which cause charge leakage and data loss.

Innovation Solution

Implementing memory activation timing management by introducing a delay between activation and pre-charge cycles for recently accessed memory cells, ensuring a sufficient wait time to prevent COP and CCP wear-out, while maintaining performance by omitting delays for non-recently accessed cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If continuous repeated access to memory cells is performed, then productivity is improved, but reliability deteriorates due to COP and CCP wear-out mechanisms

Engineering Contradiction:
Improvememory access speedVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies periodic action by introducing a delay mechanism that periodically interrupts continuous memory access operations. When a memory cell is accessed, a timer is started, and if another access to the same cell occurs before the timer expires, the access is delayed. This periodic timing control prevents continuous repeated access patterns that cause COP and CCP wear-out, while still allowing high-speed access when the timer has expired, thus resolving the contradiction between productivity and reliability.

Inventive Principle:
Principle #19Periodic action

2Reliability

If delay is introduced between activation and pre-charge cycles, then reliability is improved by preventing wear-out, but productivity deteriorates due to increased access time

Engineering Contradiction:
Improvememory cell lifespanVSAvoidmemory access throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamics by making the delay mechanism adaptive rather than fixed. The delay is dynamically applied only when needed - specifically when a memory cell is accessed again before the timer expires. For first-time accesses or accesses after the timer has expired, no delay is introduced. This dynamic conditional delay prevents the systematic performance degradation that would result from a fixed delay, while still providing protection against COP and CCP wear-out mechanisms.

Inventive Principle:
Principle #15Dynamics

3Reliability

If frequent refresh operations are performed, then data integrity is maintained, but energy consumption increases

Engineering Contradiction:
Improvecharge retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies self-service by using the natural operation flow of memory access to trigger refresh operations. Instead of implementing a separate, continuous refresh mechanism that would consume constant power, the system uses the timer mechanism already present for wear-out prevention to also handle refresh needs. When the timer expires, the memory cell is naturally re-accessed, which serves both as a refresh operation and as a normal memory access, eliminating the need for dedicated refresh power consumption.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11742002B2Memory activation timing management
Publication Date: 2023.08.29 MICRON TECHNOLOGY INC
  • US11742002B2 patent drawing
  • US11742002B2 patent drawing
  • US11742002B2 patent drawing

AI summary

Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.