Memory-Adaptive CNN Processing Reduces DRAM Access

The patent segments the feature maps into tiles and divides the convolution operation into multiple processing stages. By processing smaller tile regions sequentially and using cache memory to store intermediate results, the system reduces repeated DRAM accesses while maintaining computational completeness. This segmentation allows the processor to work with smaller data chunks that fit in cache, thereby reducing power consumption from DRAM access.

The patent implements preliminary actions by pre-loading input feature map tiles into cache memory before the actual convolution computation. By preparing and storing necessary data in advance in the cache hierarchy, the system minimizes the need for repeated DRAM accesses during the computation phase, thus reducing power consumption while maintaining processing throughput.

The patent dynamically adjusts the tile size and processing parameters based on the available cache memory capacity. By making the tile dimensions adaptive rather than fixed, the system can optimize the balance between reducing DRAM access frequency and fitting tiles within the available cache memory. This dynamic adjustment allows the same system to operate efficiently across different memory configurations.

The patent changes key parameters such as tile size, number of output groups, and processing loop structure based on the calculated size relations between input/output feature maps and cache capacity. By varying these parameters adaptively, the system optimizes cache utilization and minimizes DRAM access without requiring a fixed large cache memory, thus resolving the contradiction between power consumption and memory size requirements.

The patent segments the output channels into multiple output groups and processes them in sequence rather than all at once. This segmentation allows the system to clear and reuse cache memory between different output group processing, significantly improving cache utilization efficiency. While the computation becomes slightly more complex due to the sequential processing, the reduction in DRAM access power consumption more than compensates for this overhead.

The patent implements periodic action by processing output channels in periodic batches (output groups) with cache clearing and reuse between batches. This periodic processing pattern allows the cache memory to be efficiently utilized for each group while maintaining overall processing throughput. The system alternates between computing for one output group, writing results to memory, clearing cache, and moving to the next group, creating a rhythmic processing cycle that optimizes both throughput and power consumption.