Memory Device Adaptive Refresh Control Logic
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Solution Overview
Problem
Volatile semiconductor memory devices face data loss due to leakage currents, necessitating frequent refresh operations, which can degrade performance if excessive, or lead to data loss if infrequent.
Innovation Solution
A memory device with control logic that measures and manages a refresh count based on various events causing leakage currents, such as access frequency and periodic oscillations, to optimize refresh operations for each memory block, balancing dynamic and static leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently to prevent data loss, then data retention reliability is improved, but device performance deteriorates
Solution Approach 1:
The refresh operation frequency is made dynamic rather than fixed. The control logic adjusts the refresh interval based on detected leakage current events, performing refresh operations more frequently when leakage is detected and less frequently when stability is confirmed, thus optimizing both data retention and performance
Solution Approach 2:
A feedback mechanism is implemented where the system monitors leakage current events in memory cells and uses this information to adjust refresh operation timing. The control logic receives feedback about charge loss events and modifies refresh frequency accordingly, preventing both data loss and unnecessary performance degradation
2Productivity
If refresh operations are performed less frequently to maintain performance, then device productivity is improved, but data loss risk increases
Solution Approach 1:
The system performs preliminary detection of leakage current events and initiates refresh operations before complete data loss occurs. By monitoring charge levels and detecting early signs of leakage, the system proactively refreshes memory cells to prevent data loss while minimizing unnecessary refresh operations
Solution Approach 2:
The refresh operation parameters are changed based on actual memory cell conditions. The control logic adjusts refresh timing and frequency according to detected leakage events, transitioning from fixed periodic refresh to condition-based adaptive refresh, thereby optimizing both performance and reliability
3Device complexity
If uniform refresh operations are applied to all memory blocks, then control simplicity is maintained, but refresh efficiency decreases
Solution Approach 1:
The memory bank is divided into multiple memory blocks, each with independent refresh control. The control logic can selectively apply refresh operations to specific blocks based on detected leakage events, rather than uniformly refreshing all blocks, thereby improving refresh efficiency while maintaining manageable control complexity
Solution Approach 2:
Different refresh strategies are applied to different memory blocks based on their individual characteristics and detected leakage behavior. Blocks experiencing leakage events receive targeted refresh operations, while stable blocks operate with longer intervals, optimizing overall system efficiency
Data Source
AI summary
Disclosed is a memory device which includes a memory bank including a plurality of memory cells, and control logic controlling a data input/output operation for the plurality of memory cells. The control logic partially measures a refresh count, which is associated with the number of times of occurrence of at least one event causing a leakage current in the plurality of memory cells, with respect to the memory bank, and partially performs a refresh operation on the memory bank based on the refresh count.