Semiconductor Memory Device Adaptive Verify Voltage Control
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Solution Overview
Problem
In nonvolatile semiconductor memory devices like NAND type flash memory, maintaining the intermediate voltage distribution during data write operations is challenging due to the increase in write and erase cycles, leading to higher fail bit numbers and reduced data hold characteristics, especially when a uniform verify voltage is used regardless of the cycle count.
Innovation Solution
A control circuit that dynamically adjusts the verify voltage based on the number of write and erase cycles, using optimized verify voltages (V0, V1, V2, V3) to minimize fail bits and maintain a narrow threshold voltage distribution, and an additional pre-write and pre-verify process in the second embodiment to suppress excessive write and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform verify voltage is used regardless of write and erase cycle count, then the verify operation is simple and fast, but the fail bit number increases and data hold characteristics deteriorate
Solution Approach 1:
The verify voltage is changed dynamically based on the number of write and erase cycles. The control circuit selects different verify voltages (V0, V1, V2, V3) according to the cycle count, making the verify operation adaptive rather than static. This resolves the contradiction by allowing the system to maintain high reliability through optimized verify voltages while managing complexity through automated cycle-based selection.
Solution Approach 2:
The verify voltage parameter is changed according to the write and erase cycle count. Different verify voltage levels (V0, V1, V2, V3) are applied at different stages of the memory device's lifecycle. This parameter change strategy directly addresses the technical contradiction by optimizing data hold characteristics for different cycle conditions while maintaining a systematic approach to voltage management.
2Reliability
If the verify voltage is changed according to the number of write and erase cycles, then the fail bit number is reduced and data retention is improved, but the control complexity increases
Solution Approach 1:
The control circuit uses feedback from the cycle count to automatically select the appropriate verify voltage. The system monitors the number of write and erase cycles and adjusts the verify voltage accordingly without requiring external intervention. This feedback mechanism improves data retention while managing control complexity through automation rather than manual adjustment.
Solution Approach 2:
The memory device performs self-adjustment of verify voltage based on its own usage history (cycle count). The control circuit autonomously determines which verify voltage to apply based on the accumulated write and erase cycles, making the system self-regulating. This reduces the burden on external control systems while maintaining improved data retention.
3Manufacturing precision
If multiple verify voltages are used to optimize data hold characteristics, then the threshold voltage distribution remains narrow, but the verify operation time increases
Solution Approach 1:
The verify operation is segmented into different phases corresponding to different cycle ranges, with each phase using an optimized verify voltage (V0, V1, V2, or V3). This segmentation allows the system to maintain narrow threshold voltage distribution through precise voltage selection while minimizing total verify time by using the most appropriate voltage for each cycle stage rather than repeatedly applying all voltages.
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises: a nonvolatile memory cell capable of multi-level storage; and a control circuit that performs write control on the memory cell. The control circuit executes: a first write operation to obtain a certain intermediate voltage distribution; a second write operation to obtain a final voltage distribution; and a change operation that changes a value of the first verify voltage according to the number of times of writes and the number of times of erases on the memory cell.