Semiconductor Memory Address Buffer Pin Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices require a large number of address pins for testing, which increases test time and cost due to limited channels in test apparatuses.
Innovation Solution
The semiconductor memory device incorporates a first address buffer for both test and normal modes, receiving addresses at rising edges, and a second address buffer only in normal mode, disabled in test mode, allowing addresses to be inputted at both rising and falling edges in test mode, reducing the number of necessary address pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If addresses are received only at rising edges through dedicated address buffers for each pin, then normal operation is ensured, but the number of address pins required for testing increases
Solution Approach 1:
The first address buffer is designed to serve dual purposes: it receives addresses at rising edges during normal operation and receives addresses at both rising and falling edges during test mode. This multi-functionality allows the same buffer to handle different operational requirements, reducing the need for separate dedicated buffers for test operations and thereby reducing the number of address pins required.
Solution Approach 2:
The address buffer system dynamically switches between normal mode and test mode. In normal mode, the first address buffer operates with rising edge clock signals. In test mode, the same buffer can accept addresses at both rising and falling edges. This dynamic adaptability allows the system to optimize pin usage based on operational context, resolving the contradiction between reliability and pin quantity.
2Adaptability or versatility
If separate address buffers are provided for test mode and normal mode, then addressing flexibility is improved, but device complexity increases
Solution Approach 1:
Instead of providing separate dedicated buffers for test mode and normal mode, the invention uses a single first address buffer that can operate in both modes. The buffer's functionality is adapted through control signals that enable it to receive addresses at different clock edges depending on the operational mode, thereby maintaining versatility while reducing complexity.
Solution Approach 2:
The invention merges the test mode address buffer functionality and normal mode address buffer functionality into a single first address buffer. By combining these functions and using control logic to switch between operational modes, the system achieves the same versatility as separate buffers would provide, but with reduced device complexity.
3Reliability
If more address pins are used for testing, then test coverage is improved, but test time and cost increase
Solution Approach 1:
The first address buffer's ability to function in both normal and test modes with different clock edge requirements allows the test apparatus to use existing address pins more efficiently. During test mode, the buffer can receive addresses at falling edges in addition to rising edges, enabling comprehensive test coverage without requiring additional dedicated test pins, thereby reducing test time and cost.
Data Source
AI summary
A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode.