Semiconductor Memory Address Buffer Power Control
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Solution Overview
Problem
Conventional semiconductor memory devices incur excessive power consumption due to address buffers remaining enabled during write operation modes, even when not in use, leading to inefficient energy usage.
Innovation Solution
A semiconductor memory device with a control circuit that selectively disables unused address input blocks based on burst length information during write operations, using a control signal generator and enable signal generator to manage enable signals for different address buffers, ensuring only necessary buffers are active.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address buffers are continuously enabled to maintain readiness for address input, then the device can respond immediately to address changes, but power consumption increases due to unnecessary buffering during write operations
Solution Approach 1:
The patent applies dynamics by making the address buffer enable state changeable rather than fixed. The enable signal to the address buffer is dynamically adjusted based on the operation mode (read/write) and burst length, allowing the buffer to be enabled only when necessary for address input, thereby reducing power consumption while maintaining responsive address handling capability when needed
Solution Approach 2:
The patent changes the operational parameters of the address buffer by controlling its enable state based on operation mode and burst length parameters. By modifying the enable parameter conditionally, the system optimizes power consumption without permanently compromising address response capability, as the buffer can be re-enabled when read operations are required
2Adaptability or versatility
If all address buffers are enabled continuously to support burst ordering operations, then any address can be received immediately, but unused buffers consume unnecessary power during write operations
Solution Approach 1:
The patent segments the address buffer control into multiple independent enable signals corresponding to different address buffers. Each address buffer can be independently enabled or disabled based on whether it is needed for the current operation, allowing the system to maintain burst ordering capability for required buffers while disabling others to eliminate energy waste
Solution Approach 2:
The patent applies partial action by enabling only the specific address buffers that are needed for the current operation rather than all buffers. During write operations with certain burst lengths, only the buffers required for that specific burst pattern are enabled, avoiding the energy waste of enabling all buffers continuously while still supporting the required burst ordering operations
Data Source
AI summary
A semiconductor memory device includes a plurality of address input blocks configured to respectively receive a plurality of addresses that are related to burst ordering and a control circuit configured to selectively disable all or a part of the address input blocks in response to a burst length information during a write operation mode.