Semiconductor Memory Address Error Monitoring with ECC Flags
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Solution Overview
Problem
The increased data input/output speed in DDR2, DDR3, DDR4, and DDR5 methods leads to higher probabilities of errors during data transmission, necessitating improved methods to ensure data transmission reliability.
Innovation Solution
An electronic system with a controller and semiconductor device that includes error correction circuits and fail detection circuits to correct errors in internal data and generate a flag signal when errors are corrected a set number of times, ensuring reliable data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data input/output speed is increased to improve productivity, then operating speed is improved, but error probability during data transmission increases
Solution Approach 1:
The patent implements a feedback mechanism where the semiconductor device monitors error correction operations and generates a flag signal when errors are corrected a predetermined number of times. This feedback loop allows the system to detect and report persistent errors to the controller, enabling real-time reliability monitoring without reducing data transmission speed.
Solution Approach 2:
The error correction circuit performs self-diagnosis and self-correction by automatically detecting errors in internal data and correcting them using stored parity information. The system serves itself by monitoring its own error correction operations and generating flag signals when correction failures occur, eliminating the need for external monitoring infrastructure.
2Reliability
If error correction codes are added to ensure data transmission reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error correction function with the existing memory device structure by integrating the error correction circuit directly into the semiconductor device. The fail detection circuit is combined with the row address and column address generation circuits, allowing error monitoring to be performed within the existing architectural framework without adding separate complex monitoring systems.
Solution Approach 2:
The error correction circuit serves multiple functions: it corrects errors in internal data, monitors the correction process, generates flag signals for error detection, and provides feedback to the controller. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while maintaining high reliability.
Data Source
AI summary
An electronic system includes a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host. The electronic system also includes a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses, and the external column addresses to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times.