Memory Address Decoding Prioritization for Security

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Solution Overview

Problem

In computer systems, overlapping memory address ranges can lead to unpredictable behavior and compromise security by allowing unauthorized access to privileged software and hardware modules, as existing address decoding methods lack a systematic prioritization mechanism.

Innovation Solution

Introducing a system-wide decoding priority value for base address registers, which dictates the order of address decoding operations, ensuring that the highest priority register is used for decoding, even in cases of overlapping ranges, and allowing configuration by firmware or privileged software for enhanced security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If overlapping memory address ranges are assigned to various devices, then device flexibility and adaptability are improved, but system reliability and security are worsened due to unpredictable behavior and unauthorized access

Engineering Contradiction:
Improvedevice flexibilityVSAvoidsystem reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by assigning different decoding priorities to different base address registers based on the security sensitivity of each device. Critical devices like SMM and SGX receive higher priorities while less critical devices receive lower priorities. This localized differentiation maintains the flexibility to assign overlapping ranges while ensuring predictable decoding behavior for security-critical regions, thus resolving the contradiction between adaptability and reliability.

Inventive Principle:
Principle #3Local quality

2Device complexity

If existing address decoding methods are used without prioritization, then device complexity is reduced, but security is worsened due to lack of protection against memory remapping attacks

Engineering Contradiction:
Improveaddress decoding complexityVSAvoidsecurity vulnerability
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary action by pre-configuring decoding priorities for base address registers during system initialization. The firmware or privileged software establishes the priority order before any memory access occurs, so that when overlapping addresses are encountered, the highest priority register is automatically selected without requiring complex real-time arbitration logic. This preliminary setup enhances security against memory remapping attacks while keeping the decoding mechanism relatively simple.

Inventive Principle:
Principle #10Preliminary action

3Object-affected harmful factors

If highest priority is always assigned to SMM register, then security is improved by preventing unauthorized access, but adaptability is worsened due to restricted memory range configuration

Engineering Contradiction:
Improvesecurity protectionVSAvoidmemory range flexibility
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the priority assignment configurable rather than fixed. The firmware or privileged software can dynamically adjust which base address registers receive highest priorities based on the specific security requirements and memory mapping needs of different systems. This dynamic configurability allows the system to maintain strong security protection for critical regions like SMM and SGX while still providing the flexibility to adapt to different hardware configurations and security scenarios.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10521342B2Memory address decoding prioritization
Publication Date: 2019.12.31 INTEL CORP
  • US10521342B2 patent drawing
  • US10521342B2 patent drawing
  • US10521342B2 patent drawing

AI summary

System and methods for address decoding prioritization. An example processing system may comprise: a plurality of base address registers, wherein each base address registers specifies an address range and a decoding priority associated with the address range; and an address decoding circuit coupled to the plurality of base address registers, the address decoding circuit to: receive a memory address identified by a memory access transaction, and produce a decoded address by decoding the memory address using the plurality of base address registers in an order of respective decoding priorities.