Memory Address Conversion for Defect-Tolerant Storage Chips
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Solution Overview
Problem
Existing storage devices using variable resistance elements, such as MRAM, suffer from high defect rates in memory cells, which affect their reliability and performance.
Innovation Solution
A storage device with a first memory chip and a circuit for address conversion, utilizing a conversion function and parameters to convert input addresses, enabling access to alternative memory cells to bypass defects, thereby reducing the defect rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips from the same wafer are used to increase storage capacity, then the storage capacity is improved, but the defect rate increases because the probability of accessing defective cells increases
Solution Approach 1:
The patent applies address inversion by flipping specific bits of the address signal before accessing memory cells across multiple chips. This inversion transformation maps addresses that would normally point to defective cells in one chip to corresponding cells in other chips, effectively distributing access away from defective locations and reducing the overall defect rate while maintaining storage capacity.
Solution Approach 2:
The patent changes the address parameter by applying a bit inversion operation based on a conversion parameter. This parameter transformation modifies the address signal characteristics before it reaches the memory cell array, enabling the system to access different physical cells than would be indicated by the original address, thereby avoiding defective cells.
2Reliability
If address conversion is implemented to reduce defect rate, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent extracts the address conversion function into a separate, dedicated circuit module that operates independently from the main memory access path. This extracted conversion circuit processes only the address signals and feeds the transformed addresses to the memory cell array, isolating the complexity of address manipulation from the core storage functionality and making the system more manageable.
Solution Approach 2:
The patent introduces an address conversion circuit as an intermediary component between the address input and the memory cell array. This intermediate circuit receives the original address signals, applies the bit inversion transformation, and outputs the converted addresses to the memory array, thereby mediating the interaction between the control logic and the storage elements.
Data Source
AI summary
According to one embodiment, there is provided a storage device comprising a first memory chip that includes a plurality of first memory cells and that includes a first circuit configured to perform address conversion by using a conversion function; and a second circuit that is connected to the first memory chip and that is configured to set a first parameter for the first memory chip, wherein when a first address is transmitted to the first memory chip from the second circuit, the first address is converted into a second address by the conversion function using the first parameter, and then one of the plurality of first memory cells that corresponds to the second address in the first memory chip is accessed.