Semiconductor Memory Address Delay Unit Power Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices experience unnecessary power consumption due to the continuous operation of flip-flops in address generation units, which delays external addresses by predetermined times, even when no valid address is being inputted, leading to idle and active state power wastage.
Innovation Solution
A semiconductor memory device is designed with a command decoding unit, a driving signal generation unit, and an address delay unit that synchronizes internal address signals with driving signals generated from the activation timing of a CAS signal, reducing power consumption by operating only during valid address inputs and using fewer clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip-flops in address generation units continuously operate to delay external addresses by predetermined times, then address timing control is achieved, but power consumption increases during idle and active states
Solution Approach 1:
The patent applies periodic action by controlling the address delay unit to operate only during specific periods when valid addresses are inputted, rather than continuous operation. The control signal enables the delay unit to function periodically in sync with command signals, reducing power consumption during idle periods while maintaining address timing control when needed.
Solution Approach 2:
The patent implements dynamics by making the address delay unit's operation state changeable between active and idle modes based on input conditions. The control signal dynamically enables or disables the delay unit's operation, allowing the system to adapt its power consumption levels according to the actual need for address processing.
2Measurement precision
If address delay unit operates continuously to synchronize internal address signals, then timing precision is maintained, but unnecessary power is consumed when no valid address is inputted
Solution Approach 1:
The address delay unit is controlled to operate periodically only when valid addresses are inputted, as indicated by control signals generated from command decoding. This periodic operation maintains timing precision during active periods while avoiding energy waste during idle periods when no address processing is required.
Solution Approach 2:
The patent extracts the address delay function from continuous operation and activates it only when needed. The control signal mechanism separates the delay functionality from constant operation, enabling the system to take out the address processing task from the continuous operational context and execute it selectively based on actual input conditions.
3Adaptability or versatility
If multiple address shifting units are used to generate internal column addresses with different delay times, then address flexibility is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single address delay unit that can handle multiple address shifting requirements through variable delay control. Instead of having separate dedicated shifting units for different delay times, one multi-functional delay unit is controlled to provide the necessary timing variations, reducing overall device complexity while maintaining address flexibility.
Solution Approach 2:
The patent implements parameter changes by controlling the delay amount of the address delay unit dynamically based on the type of operation (read or write) and command timing requirements. By changing the delay parameter rather than using fixed separate units, the system achieves address flexibility with reduced hardware complexity.
Data Source
AI summary
The present invention provides a semiconductor memory device for reducing a power consumption. A semiconductor memory device includes a command decoding unit for decoding a plurality of commands; a driving signal generation unit for generating a plurality of driving signals synchronized with Nth clocks of an internal clock from an activation timing of a CAS signal generated by the command decoding unit, wherein N is an even integer number; an address delay unit for receiving an internal address in response to the CAS signal and for delaying the internal address signal by synchronizing the internal address with the plurality of driving signals; and a data access block for performing a data access in response to the delayed internal address.