Memory Address Verification Using Error Detection Bits
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Solution Overview
Problem
Memory devices may inadvertently store or retrieve data from incorrect addresses, leading to incorrect data being returned to the host device, which can negatively impact system performance.
Innovation Solution
The memory device generates and communicates an address match signal by using error detection bits based on write and read addresses to verify address matching, allowing the host device to determine if the returned data is correct.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device uses traditional address storage and retrieval methods, then the device complexity is low, but the reliability of address matching is insufficient leading to potential incorrect data retrieval
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing error detection bits (EDBs) for write addresses before actual data storage. When a read operation occurs, the system retrieves both the stored EDBs and calculates EDBs for the read address, then compares them to verify address matching. This advance preparation of verification data enables reliable address checking without adding complex real-time verification hardware.
Solution Approach 2:
The patent introduces error detection bits as an intermediary element that mediates between the address bus and the data retrieval process. These EDBs serve as a verification layer that compares write and read addresses without requiring direct complex address matching logic. The EDBs act as a simple binary comparator that indicates whether addresses match, thereby simplifying the overall verification mechanism while improving reliability.
2Reliability
If the memory device implements address verification using error detection bits, then the reliability of data retrieval is improved, but the loss of time due to additional verification operations increases
Solution Approach 1:
The patent reduces verification time by performing preliminary actions during the write operation. Error detection bits are calculated and stored alongside the data at the write address before the read operation occurs. This pre-computation means that during read operations, the system only needs to retrieve pre-stored EDBs and compare them with newly calculated EDBs, rather than performing complex verification from scratch, thereby minimizing additional verification time.
Solution Approach 2:
The patent applies local quality by implementing address verification only where and when needed through the EDB comparison mechanism. Rather than verifying every address access uniformly, the system selectively verifies addresses by comparing EDBs, which are locally stored with the data. This localized verification approach minimizes the time impact on routine operations while maintaining reliability for critical data retrieval.
3Measurement precision
If the memory device stores error detection bits for each address, then the address verification accuracy is improved, but the quantity of stored information increases
Solution Approach 1:
The patent extracts only the essential verification information needed for address matching by storing error detection bits rather than complete address copies. The EDBs are condensed representations derived from the full address through error detection algorithms, capturing only the critical verification elements. This extraction approach maintains high verification accuracy while minimizing the additional storage requirements compared to storing full address data.
Solution Approach 2:
The patent transforms the address parameter into a condensed error detection bit representation. Instead of storing and comparing full address values, the system converts addresses into EDBs through mathematical transformations (such as parity bits or checksum calculations). This parameter change reduces the storage burden from full address width to a smaller verification code width while preserving the ability to accurately verify address matching through the transformed parameter.
Data Source
AI summary
Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.