Memory Address Error Detection Using DRAM-Generated EDC
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Solution Overview
Problem
Modern memory systems face challenges in detecting and correcting errors, particularly address errors, which can lead to data corruption due to increasing data transfer rates and noise-related issues.
Innovation Solution
The implementation of an error-detection code (EDC) mechanism in memory systems, where the DRAM computes an EDC based on received addresses and data, and transmits it back to the controller for verification, allowing for error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then productivity is improved, but transmission errors increase due to noise and signal quality degradation
Solution Approach 1:
The patent applies preliminary action by computing the error-detection code at the transmitter side before data transmission, and preparing the verification mechanism at the receiver side. The EDC is calculated in advance using cryptographic hash functions (SHA-1, SHA-256, or SHA-512) on the outgoing data and address, and the receiver is prepared to verify this code after reception, enabling proactive error detection before data corruption occurs.
Solution Approach 2:
The patent implements feedback by transmitting the error-detection code along with the data and address information, and then verifying this code at the receiver side. The verification result provides feedback on the integrity of received data, allowing the system to detect transmission errors caused by high-speed noise and signal degradation, thus closing the reliability loop.
2Reliability
If error detection mechanisms are added to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by using cryptographic hash functions (SHA-1, SHA-256, SHA-512) that serve multiple purposes: they provide error detection capability, data integrity verification, and can be configured for different security requirements. The same EDC mechanism handles both address and data verification, reducing the need for separate error detection systems and simplifying the overall device architecture.
Solution Approach 2:
The patent implements parameter changes by allowing the selection of different hash function algorithms (SHA-1, SHA-256, SHA-512) with varying computational complexity and security levels. This enables the system to adjust the error detection mechanism's strength according to specific application requirements, balancing reliability needs against device complexity and performance constraints.
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.