Memory Address Error Detection Using DRAM EDC Feedback
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and inter-symbol interference, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
The implementation of a mechanism in memory systems where DRAM computes an error-detection code (EDC) based on both address and data, which is then verified by the memory controller, allowing for the detection and prevention of erroneous write operations by canceling them, thus ensuring error-resistant transmission of both address and data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then productivity is improved, but signal quality deteriorates due to noise and inter-symbol interference
Solution Approach 1:
The patent applies preliminary action by computing error-detection codes (EDC) for both address and data before transmission. The memory controller calculates EDC values for the address and data portions separately, then transmits them to the memory device. This allows error detection to be prepared in advance, enabling the system to maintain high data transfer rates while ensuring signal integrity through pre-computed error detection mechanisms.
2Reliability
If error detection mechanism is added to detect address errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error detection mechanism into separate components for address and data portions. The memory controller computes EDC values separately for address and data, and the memory device separately verifies each. This segmentation allows the system to detect address errors specifically without requiring a completely new complex system, as each portion is handled independently with its own EDC verification process.
3Measurement precision
If separate EDC verification for address and data is implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements segmentation by creating separate verification paths for address and data portions. The memory device receives separate EDC values for address and data, verifies them independently, and can identify whether an error occurred in the address portion, data portion, or both. This segmented approach improves measurement precision by enabling specific error location while managing complexity through modular verification processes.
Solution Approach 2:
The patent applies universality by using the same EDC computation and verification methodology for both address and data portions. The memory controller and memory device use consistent EDC algorithms for both portions, allowing a single verification mechanism to serve multiple functions (address verification and data verification). This multi-functional approach improves detection precision across different data types while avoiding the need for entirely separate complex verification systems.
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.