Memory Address Engine for Non-Contiguous Data Streams
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Solution Overview
Problem
Modern microprocessor architectures face inefficiencies in memory address generation, particularly when dealing with complex or non-contiguous memory address calculations, which can significantly reduce processing power and increase power consumption, especially in applications like medical imaging and vector processing.
Innovation Solution
A method and system for generating a stream of non-contiguous memory addresses using an external memory address engine, initialized with parameters describing contiguous points in logical space, allowing the CPU to focus on data processing rather than address generation, and utilizing multiple memory address engines for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CPU generates memory addresses for complex non-contiguous data patterns, then processing flexibility is maintained, but processing speed decreases and power consumption increases
Solution Approach 1:
The patent extracts the memory address generation function from the CPU by introducing a dedicated address generation unit (AGU). This specialized unit handles complex non-contiguous address patterns independently, allowing the CPU to focus on data processing while the AGU manages address calculation, thereby resolving the contradiction between processing flexibility and speed.
Solution Approach 2:
The address generation unit serves as an intermediary component between the CPU and memory system. It receives processing parameters from the CPU, generates the corresponding memory addresses, and returns results to the CPU, enabling complex address patterns to be handled without burdening the main processing unit.
2Speed
If execution units are dedicated to memory address generation, then address processing speed improves, but overall CPU processing power decreases
Solution Approach 1:
The patent segments the CPU functionality by creating a separate address generation unit that operates independently from the main execution units. This segmentation allows address generation to occur in parallel with data processing, improving address processing speed without reducing overall CPU processing power since the execution units remain available for their primary functions.
Solution Approach 2:
The address generation unit is designed as a multi-functional component that can handle various addressing modes (contiguous, non-contiguous, strided, scattered) within a single unified structure. This universal design provides dedicated address processing capability without requiring multiple specialized execution units, preserving CPU processing power while improving address generation speed.
3Productivity
If multiple execution units are allocated to address generation, then parallel address processing improves, but device complexity and power consumption increase
Solution Approach 1:
The patent merges multiple address generation functions into a single unified address generation unit that can operate in parallel modes. Rather than implementing separate execution units for different addressing tasks, the AGU integrates all address generation capabilities and can process multiple addresses simultaneously through internal parallelization, achieving parallel address processing without increasing device complexity.
4Device complexity
If the CPU handles memory paging and address generation, then system simplicity is maintained, but data waiting time increases
Solution Approach 1:
The patent extracts the address generation and paging management functions from the CPU by introducing a dedicated address generation unit. This unit operates independently to generate memory addresses and manage paging operations, eliminating the need for the CPU to wait during address calculation and reducing data waiting time while maintaining relatively simple system architecture.
Solution Approach 2:
The address generation unit performs preliminary address generation and memory paging operations before the CPU needs the data. By pre-calculating addresses and preparing data transfers in advance, the system reduces the time the CPU spends waiting for memory operations to complete.
Data Source
AI summary
A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.