Semiconductor Memory Address Translation Error Correction
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Solution Overview
Problem
Semiconductor memory devices with nonvolatile memory, such as NAND-type flash memory, face errors in address translation tables due to soft errors caused by miniaturization, which complicates wear leveling and data recording processes.
Innovation Solution
Incorporating a check code generating unit to generate error check codes and a correcting code generating unit to correct errors in the address translation table, along with a translating unit that uses an address translation table to translate logical addresses to physical addresses, and storing redundant data with user data to identify and correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the address translation table is stored in a volatile memory such as SRAM or DRAM, then the addressing architecture control is enabled for wear leveling, but soft errors occur more frequently due to miniaturization of semiconductor manufacturing processes
Solution Approach 1:
The patent applies preliminary action by generating check codes (such as parity bits or ECC codes) for the address translation table entries before they are stored in the volatile memory. This preventive measure allows the system to detect and correct errors before they affect data retrieval operations, thus maintaining reliability while enabling addressing architecture control.
Solution Approach 2:
The patent introduces check codes as an intermediary element between the address translation table and the volatile memory storage. These check codes serve as a mediator that enables error detection and correction without interfering with the primary function of address translation, thus resolving the contradiction between versatility and reliability.
2Reliability
If error check codes and redundant data are generated and stored with user data, then error detection and correction capability is improved, but the storage capacity available for user data is reduced
Solution Approach 1:
The patent applies partial action by implementing error check codes only for critical data structures such as the address translation table, rather than for all stored data. This selective approach provides sufficient error protection for the most vulnerable components while minimizing the overhead on overall storage capacity.
Solution Approach 2:
The patent employs parameter changes by using efficient error coding schemes such as parity bits or lightweight ECC codes that provide adequate error detection and correction with minimal redundancy. By optimizing the code parameters, the system achieves reliable error protection while preserving maximum storage capacity for user data.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a nonvolatile memory; an input/output control unit to control input/output of data to/from the nonvolatile memory; an address translation table that associates first address information specifying a logical recording position of user data stored in the nonvolatile memory with second address information indicating a physical recording position in the nonvolatile memory; a translating unit to translate the first address information to the second address information according to the table; and a generating unit to generate redundant data for checking whether there is error in the user data and the first address information used as one data piece. The input/output control unit records, as data set, the user data, the first address information, and the redundant data, which are used as one data set, in the physical recording position in the nonvolatile memory indicated by the second address information.