Semiconductor Memory Address Input Path Selection Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices require a large circuit area due to numerous delay elements in address input path selection circuits, which can lead to malfunctions as Y-address input enable signals are activated regardless of the bank state, causing operational issues during read/write operations.
Innovation Solution
The semiconductor memory device incorporates address input path selection circuits with a signal input unit that activates Y-address input enable signals based on bank-specific read/write signals and a latch unit that operates only when a bank is active, eliminating the need for internal read and write signals and reducing the requirement for delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional address input path selection circuits are used with numerous delay elements, then the circuit can generate Y-address input enable signals, but the circuit area becomes large and malfunctions occur when signals are activated regardless of bank state
Solution Approach 1:
The patent extracts and eliminates the unnecessary internal read and write signals from the address input path selection circuit. By removing these redundant signals and the associated delay elements, the circuit area is reduced while maintaining reliable operation through the simplified signal path that only uses bank-specific read/write signals.
Solution Approach 2:
Instead of using internal read and write signals to control the address input path selection, the patent inverts the approach by using bank-specific read/write signals directly. This inversion eliminates the need for delay elements and prevents malfunctions by ensuring signals are only activated when the corresponding bank is actually active.
2Device complexity
If address input path selection circuits operate without bank state checking, then the circuit structure is simpler, but malfunctions occur when Y-address input enable signals are activated regardless of bank state
Solution Approach 1:
The patent implements feedback by using the bank active signal to control the enablement of the address input path selection circuit. The bank-specific read/write signals are only processed when the corresponding bank is active, creating a feedback mechanism that prevents malfunctions while maintaining relatively simple circuit structure through the use of standard logic gates.
Data Source
AI summary
A semiconductor memory device having banks includes an address input path selection circuit in each of the banks, the address input path selection circuit including a signal input unit configured to selectively activate a Y-address input enable signal in response to a bank-specific read/write signal, and a latch unit configured to latch the Y-address input enable signal. The address input path selection circuit reduces circuit area by reducing delay elements and prevents malfunction by operating only in a bank active state.