Memory Controller Address Integrity Checking Across Split Transactions
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Solution Overview
Problem
Existing memory controllers do not provide adequate address integrity protection for data words throughout the entire address path, leaving portions outside split-addressed processing vulnerable to address corruption, which can lead to undetected errors in memory transactions.
Innovation Solution
A memory controller system and method that includes a communication port, an interface portion, and an address protection portion to adaptively convert and maintain address integrity by detecting errors through comparison of output addresses over multiple clock cycles, ensuring address protection from the user interface ports to the memory device, using adaptive split addressing and parity checks where feasible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address protection measures are implemented throughout the entire address path, then address integrity is improved, but device complexity increases
Solution Approach 1:
The address path is segmented into distinct portions: the interface portion containing adaptation stages, and the command control portion with split-address processing. Address protection is applied selectively to the interface portion through stable address checking, while the command control portion relies on its inherent split-addressing redundancy. This segmentation allows protection without requiring complex measures throughout the entire controller.
Solution Approach 2:
Instead of implementing 100% address checking throughout the entire address path, the patent applies stable address checking only to the interface portion where addresses are adapted. The command control portion uses its inherent split-addressing mechanism which provides sufficient protection for its specific functions. This partial action approach maintains adequate reliability while avoiding unnecessary complexity.
2Reliability
If stable address checking is performed over multiple clock cycles, then address error detection is improved, but productivity decreases
Solution Approach 1:
The memory transaction process is segmented into phases: address adaptation in the interface portion (where stable address checking occurs over multiple clock cycles), and command execution in the command control portion. By localizing the multi-cycle checking to only the address adaptation phase, the patent maintains high productivity during the more time-sensitive command execution phases while still achieving reliable error detection.
Solution Approach 2:
Stable address checking is performed periodically over specific clock cycles (at least two consecutive cycles) during the address adaptation phase, rather than continuously throughout the entire transaction. This periodic verification approach provides sufficient error detection capability while minimizing the impact on overall transaction throughput.
Data Source
AI summary
A system and method are provided to control error-protected access to a memory device having address integrity protection for data words of memory transactions. A communication port receives a command having a port address, which is adaptively converted to a memory address by an interface portion. The interface portion includes an adaptation stage carrying out a predefined adaptation response on an address propagated therethrough during a clock cycle of operation. An address protection portion configures the adaptation stage to maintain the predefined adaptation response over at least two clock cycles. Address error is detected based on comparison of output addresses respectively generated upon iterative propagation of the same input address through the adaptation stage over the clock cycles. A command control portion executes to adaptively split each command received from the interface portion, as well as the corresponding memory address according to an inline storage configuration of the memory device.