Memory Address I/O Circuit Bubble Interval Reduction
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Solution Overview
Problem
Semiconductor memory devices face inefficiencies due to the frequency difference between reference and data clocks, leading to bubble intervals during data burst operations, which affect memory operation efficiency and performance.
Innovation Solution
A memory device with an internal command generator and address I/O circuit that generates internal commands and selects storage paths based on bubble intervals, allowing for controlled output and storage of addresses within specific clock cycles, thereby minimizing bubble intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reference clock frequency is used for memory operations, then memory operation stability is maintained, but bubble intervals occur during data burst operations reducing efficiency
Solution Approach 1:
The patent applies dynamics by making the address storage location configurable between two latches based on operational mode. The system dynamically switches between latch 0 and latch 1 for address storage depending on whether burst operations are enabled, allowing the memory device to adapt its internal timing to eliminate bubble intervals while maintaining stable reference clock operation.
Solution Approach 2:
The patent changes the parameter of address storage timing by selecting different latches (latch 0 or latch 1) based on the burst operation mode. This parameter change allows the system to adjust its internal timing characteristics to match either reference clock or data clock frequencies, thereby eliminating unnecessary idle periods during data bursts.
2Productivity
If address is stored in fixed latch location, then circuit simplicity is maintained, but address output timing cannot be optimized for different operation modes
Solution Approach 1:
The patent implements universality by designing the address I/O circuit to handle multiple operation modes through a single configurable structure. The same address I/O circuit can store addresses in either latch 0 or latch 1 depending on the burst operation mode, making the circuit multi-functional without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The patent applies dynamics by making the address storage location configurable between two latches based on operational mode. The system dynamically switches between latch 0 and latch 1 for address storage depending on whether burst operations are enabled, allowing the memory device to adapt its internal timing to eliminate bubble intervals while maintaining stable reference clock operation.
3Reliability
If internal command generation is synchronized with reference clock, then command timing stability is ensured, but address timing cannot be aligned with data burst operations
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a configurable latch selection system that mediates between the reference clock-synchronized internal commands and the data clock-synchronized data bursts. By selecting appropriate latches based on operational mode, this intermediary enables proper timing alignment without disrupting the stability of command generation.
Data Source
AI summary
A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.