Semiconductor Memory Address Latch Segmentation
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Solution Overview
Problem
As semiconductor memory devices become highly integrated, the complexity of row decoders increases due to the growing bit number of row addresses, leading to a wider circuit area requirement for address latch units, which hinders further integration.
Innovation Solution
The semiconductor memory device employs a common address latch unit to select and output latched addresses to word line driver units, reducing the number of address latch units needed and minimizing circuit area by sharing latched local address signals across multiple cell blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the row address bit number increases to support higher integration, then the storage capacity increases, but the row decoder complexity and circuit area increase
Solution Approach 1:
The row address is segmented into two parts: a first address for selecting group driving circuits and a second address for selecting unit driving circuits. This segmentation divides the complex decoding task into two simpler stages, reducing the complexity of the row decoder while supporting higher integration.
Solution Approach 2:
The address latch units are distributed across multiple banks rather than being集中 in a single location. This spatial distribution across different dimensions (banks) reduces the circuit area required for address latch units in each bank while maintaining the functionality for higher capacity devices.
2Quantity of substance
If the row address bit number increases, then the storage capacity increases, but the circuit area for address latch units increases
Solution Approach 1:
Adjacent banks share common address latch units for latching the first address. This merging of resources across banks reduces the total circuit area required for address latch units while supporting higher storage capacity through increased banking.
Solution Approach 2:
The address latch units are designed to serve multiple functions: they latch addresses for multiple cell blocks within a bank and are shared by adjacent banks. This multi-functionality reduces the overall number of latch units needed, decreasing circuit area while supporting higher integration.
3Adaptability or versatility
If more address latch units are provided to handle increased address bits, then the address decoding capability improves, but the device complexity increases
Solution Approach 1:
The address decoding is segmented into two stages using different latch units: common address latch units for the first address and individual address latch units for the second address. This segmentation provides the necessary adaptability for increased address bits while keeping each stage relatively simple.
Solution Approach 2:
The address latch structure is extended across multiple banks in a dimensional sense, allowing the same latch unit design to handle increased address capacity through replication and sharing across banks rather than increasing complexity within a single bank.
Data Source
AI summary
A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving circuits for driving N word lines of a cell block, the N unit driving circuits being divided into M group driving circuits; a common address latch unit for latching a first address for selecting one of the M group driving circuits of the word line driver unit, and outputting the latched first address to the word line driver unit; and an address latch unit for latching a second address for selecting a unit driving circuit of the selected group driving circuit in the word line driver unit, and outputting a latched second address to the word line driver unit.