Memory Address Encoding That Preserves Locality and Cuts Bus Toggling
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Solution Overview
Problem
Existing memory address encoding methods are limited in scope and lead to increased power consumption due to address bus toggling across the memory subsystem hierarchy, and duplication of encoding logic in each memory macro.
Innovation Solution
Implement address encoding upstream of the memory subsystem, specifically at the processor side, to reduce address bus toggling across the entire memory hierarchy while preserving memory access locality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If address encoding is implemented downstream at each memory macro, then address bus toggling of individual memory macros is reduced, but encoding logic is duplicated across multiple memory macros increasing power consumption
Solution Approach 1:
The address encoding function is extracted from individual memory macro address mappers and relocated to the processor-side address generation unit. This centralizes the encoding logic in a single location, eliminating duplication across multiple memory macros while maintaining the power-saving benefit of reduced address bus toggling.
Solution Approach 2:
The processor-side address generation unit is designed to perform both address encoding and base address generation functions universally for all memory macros. This single unit serves the entire memory subsystem, replacing the need for separate encoding logic in each memory macro.
2Device complexity
If address encoding is implemented upstream at the processor side, then encoding logic duplication is avoided, but memory access patterns may change causing additional address changes crossing memory macros
Solution Approach 1:
The address encoding is designed with awareness of individual memory macro base addresses and access patterns. The encoding process considers the specific characteristics of each memory macro to minimize address changes that would cross macro boundaries, applying localized optimization rather than uniform encoding.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor memory access patterns and adjust encoding decisions accordingly. This allows the address generation unit to optimize encoding in real-time, reducing unnecessary address changes across memory macro boundaries while maintaining the benefits of centralized encoding.
3Reliability
If base address is added to each system address in incremental access patterns, then correct memory macro addressing is achieved, but the number of toggled address bits increases power consumption
Solution Approach 1:
The base address is pre-incorporated into the address encoding process at the processor side before addresses are sent to memory macros. This preliminary action ensures correct addressing while minimizing subsequent address changes, as the base address information is already embedded in the encoded addresses.
Solution Approach 2:
The system uses gray code encoding which changes only one bit at a time between sequential addresses, fundamentally changing the parameter representation of addresses. This encoding scheme maintains reliable memory macro addressing while minimizing the number of bits that toggle, thereby reducing power consumption.
Data Source
AI summary
A method and device are provided in which the memory subsystem receives a range of system addresses. An address encoder of the memory subsystem encodes the system addresses to generate encoded system addresses. A first number of least significant bits (LSBs) subject to change in encoding each of the system addresses in the range is based on a lesser of a second number of trailing 0s in a binary representation of the base address and a third number of trailing 0s in a binary representation of a fourth number of the system addresses in the range. In encoding the system addresses, bit values of remaining bits in the encoded system addresses are equal to corresponding bit values in the system addresses.