Semiconductor Memory Address Mapping for Burst Mode Read Speed
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in performing half-page read operations in burst mode due to the sequential disposition of memory cell arrays, which leads to increased read time and deterioration of overall performance, as they struggle to access spare pages efficiently after main pages without exiting burst mode.
Innovation Solution
The semiconductor memory device employs an address mapping circuit that maps external addresses to internal addresses, allowing for efficient access to memory cell arrays in burst mode and common column address decoding without increasing device size, by dividing the memory cell array into multiple regions and using an address mapping unit to convert external addresses into internal addresses based on comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If memory cell arrays are sequentially disposed with main pages and spare pages in conventional order, then common column address decoding operation is enabled, but half-page read operation in burst mode cannot be performed efficiently
Solution Approach 1:
The patent divides the memory cell array into multiple blocks (first block, second block, etc.) where each block contains both main cell arrays and spare cell arrays. This segmentation allows the system to organize memory pages in a way that enables efficient burst mode access while maintaining common decoding capabilities.
Solution Approach 2:
The patent introduces a new address mapping dimension by using block-specific offset addresses combined with block selection signals. This dimensional approach allows sequential access to spare pages following main pages in burst mode without disrupting the common column address decoding structure.
2Productivity
If memory cell arrays are rearranged to enable half-page read operation in burst mode, then read speed is improved, but common column address decoding operation becomes difficult
Solution Approach 1:
The patent designs the address mapping unit to perform multiple functions: it can map addresses for common column address decoding operation and simultaneously support burst mode half-page read operations. The block selection signal and block-specific offset address system provides universal address mapping capability across different operation modes.
Solution Approach 2:
The patent implements dynamic address mapping where the mapping relationship between external addresses and internal addresses changes based on the operation mode. The address mapping unit dynamically selects appropriate mapping schemes depending on whether common decoding or burst mode operation is required.
3Productivity
If address mapping unit is added to map external addresses to internal addresses, then half-page read operation in burst mode is enabled, but device complexity increases
Solution Approach 1:
The address mapping unit is segmented into multiple components working together: block selection signal generation, block-specific offset address mapping, and external to internal address conversion. This segmentation allows each component to perform a specific function with simpler logic, reducing overall circuit complexity while enabling burst mode operation.
Solution Approach 2:
The patent introduces block-specific offset addresses as an intermediary between external addresses and internal addresses. This intermediary layer simplifies the address mapping process by providing a structured intermediate representation that facilitates both common decoding and burst mode access without requiring complex direct mapping logic.
4Area of stationary object
If sequential disposition of memory cell arrays is maintained, then device size is minimized, but read time increases and performance deteriorates
Solution Approach 1:
The patent reorganizes memory cell arrays by introducing a block dimension, where multiple blocks are disposed in a structured manner. This dimensional reorganization enables faster access to spare pages following main pages without increasing the overall device footprint, as the blocks are efficiently packed within the available area.
Solution Approach 2:
By segmenting the memory into blocks with specific arrangements of main and spare cell arrays, the patent enables more efficient spatial utilization. This segmentation allows read operations to access sequentially disposed pages within blocks more quickly, reducing read time while maintaining compact device dimensions.
Data Source
AI summary
Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device. The semiconductor memory device may include a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to an internal address, and an address mapping unit configured to map external address as the internal address when the external address designates the first main and spare cell arrays, and to operate calculation with a given value and the external address and to map the calculation result value as the internal address when the external address designates the second main and spare cell arrays.