Memory Address Mapping Cube Grouping
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Solution Overview
Problem
Resistive memory devices face data loss due to resistance drift over time, leading to increased access times when consecutive addresses are accessed, as the system must account for data recovery time in incremental address decoding schemes.
Innovation Solution
An address mapping method that groups memory cells into cubes, allocating most significant bits for cube identification and least significant bits for cell location within cubes, allowing for efficient translation between logical and physical addresses using a mapping table, thereby reducing the need for consecutive address access and minimizing data recovery time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If incremental address decoding scheme is used to access memory cells, then address translation is simplified, but access time increases due to data recovery time requirements
Solution Approach 1:
The patent segments the memory cell array into multiple banks, where each bank is independently addressable. This segmentation allows parallel access to different banks, eliminating the sequential dependency that causes access time delays in incremental decoding schemes while maintaining address translation simplicity within each bank.
2Productivity
If same row address or column address is consecutively accessed, then address pattern is simplified, but data recovery time must be secured increasing access time
Solution Approach 1:
The patent introduces bank address bits as an intermediary layer between the row/column address decoding and the physical memory cell selection. By inserting this intermediate addressing stage, the system can redirect consecutive access patterns to different banks, avoiding the need to wait for data recovery in the same bank while maintaining simple address generation logic.
Data Source
AI summary
Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (MSB) N bits of a physical address for identifying the cubes; allocating least significant bit (LSB) M bits of the physical address for designating locations of memory cells included in each of the cubes, M and N being positive integers; storing information about a mapping between a logical address and the (M+N)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.