Stacked Memory Address Mapping for Direct SRAM Access
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Solution Overview
Problem
Existing memory devices face challenges in achieving high bandwidth due to limitations in processing speed, leading to a bottleneck in overall system performance improvements.
Innovation Solution
The proposed solution involves a storage system that includes a stack of memory dies, where a host device can directly access both DRAM and SRAM memories using extended high bandwidth memory protocols, allowing for improved bandwidth without modifying the existing pinout of the memory package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory interfaces are used for stacked memory systems, then existing memory architectures can be maintained, but the increasing number of memory devices creates excessive complexity in address decoding and control logic
Solution Approach 1:
The patent divides the address space into multiple segments, with each memory device receiving a portion of the address bits. The interface controller segments the address bus into device-select lines and column-address lines, allowing each memory device to be independently addressed without requiring complex decoding logic for the entire memory array.
Solution Approach 2:
The patent introduces a new dimension to the address decoding scheme by using three-dimensional stacked memory architecture with vertical interconnects (TSVs). This adds a vertical dimension to address decoding, allowing memory devices to be addressed not only by horizontal address bits but also by their vertical position in the stack, thereby simplifying the overall decoding complexity.
2Quantity of substance
If more memory devices are stacked to increase capacity, then memory storage capacity increases, but signal integrity and timing control become more difficult
Solution Approach 1:
The patent introduces an interface controller as an intermediary between the memory controller and the stacked memory devices. This intermediary manages signal routing, timing synchronization, and data validation across multiple memory devices, ensuring signal integrity is maintained despite the increased number of devices in the stack.
Solution Approach 2:
The patent implements preliminary action by performing address validation, data parity checking, and timing synchronization in the interface controller before data is written to or read from the memory devices. This preliminary processing ensures that signals are properly conditioned and validated before reaching the memory array, maintaining reliability as stack depth increases.
3Adaptability or versatility
If traditional address decoding methods are used, then existing control logic can be maintained, but scalability to large numbers of memory devices is limited
Solution Approach 1:
The patent implements a universal interface controller design that can manage multiple types of memory devices (e.g., different capacities, speeds, or technologies) through a standardized interface. This multi-functional approach allows the same control logic to scale across different memory configurations without requiring device-specific decoding logic, thereby improving scalability while controlling complexity.
4Area of stationary object
If memory devices are closely packed in stacked architecture, then space efficiency increases, but heat dissipation and electrical interference become more severe
Solution Approach 1:
The patent applies local quality by implementing heat dissipation management at the device level rather than system level. Each memory device in the stack is designed with localized thermal management features, and the interface controller selectively activates or deactivates specific memory devices based on thermal conditions, allowing heat dissipation to be managed locally without compromising overall space efficiency.
Data Source
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AI summary
Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. The logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.