Server Memory Address Masking for Fault Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern server systems face increased memory fail rates and costs due to the growing number of processors, necessitating enhanced memory fault tolerance without the need for physical replacement of memory devices.
Innovation Solution
The implementation of a memory-test component that detects memory errors, determines physical memory addresses corresponding to bad dies, and masks these addresses from access by the operating system and other components, allowing for dynamic reservation of memory for error correction and data mirroring without physically replacing memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of memory modules is increased to accommodate more processors, then processing capability is improved, but memory fail rate increases
Solution Approach 1:
The patent segments the memory device into usable and unusable portions by identifying and masking specific bad dies at the granular level. Instead of treating the entire memory device as a single unit, the system divides it into functional segments (good dies) and non-functional segments (bad dies), allowing partial utilization of the memory device while maintaining system reliability.
Solution Approach 2:
The patent changes the parameter of memory address accessibility by dynamically masking specific physical memory addresses corresponding to bad dies. The system modifies the memory topology parameters and updates data structures (such as setting unusable memory ranges in the page table) to prevent access to faulty regions, thereby transforming the memory device from a fully accessible state to a selectively accessible state that excludes defective areas.
2Reliability
If the entire memory device is replaced when a memory error is detected, then system reliability is improved, but system cost and downtime increase
Solution Approach 1:
The patent extracts and removes only the defective portions (bad dies) from the memory device by masking their physical addresses. Instead of replacing the entire memory device, the system identifies the specific unusable memory regions and isolates them through address masking, allowing the remaining functional memory to continue operating without interruption.
Solution Approach 2:
The patent creates a modified view of the memory topology that excludes bad dies by updating data structures such as the page table to mark unusable memory ranges. This logical copying or replication of memory management structures allows the system to present a corrected memory map to the operating system without physically replacing hardware components.
3Reliability
If the entire memory device is replaced when a memory error is detected, then system reliability is improved, but system downtime increases
Solution Approach 1:
The patent performs preliminary identification and masking of bad dies during system initialization or memory testing phases before they cause system failures. By proactively detecting and isolating defective memory regions in advance, the system prevents future errors from occurring, thereby maintaining continuous operation and avoiding unplanned downtime.
Solution Approach 2:
The patent implements a dynamic memory management approach where the memory topology is updated in real-time based on detected errors. The system can dynamically adjust the mask of unusable memory addresses during runtime, allowing continuous operation with adaptive error handling rather than requiring static pre-planning or physical replacement procedures.
4Reliability
If physical memory addresses corresponding to bad dies are masked from access, then memory fault tolerance is improved, but memory capacity is reduced
Solution Approach 1:
The patent segments the memory address space into usable and unusable regions, allowing the system to precisely isolate only the defective portions. This segmentation enables the majority of the memory device (good dies) to remain accessible and functional, minimizing the impact on total memory capacity while maximizing fault tolerance.
Data Source
AI summary
Various examples of the present technology provide systems and methods for testing whether there is any memory error in a server system, determining physical memory addresses corresponding to a detected memory error on one or more memory devices of the server system, and preventing the physical memory addresses corresponding to the detected memory error from accessing by an operating system, application programs, and/or other components of the server system.