Semiconductor Memory Address Multiplexing for Terminal Load Balance
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Solution Overview
Problem
Existing semiconductor memory devices with 32-bit data width require lengthy and costly development, and using two 16-bit chips to achieve this results in uneven loads on external terminals.
Innovation Solution
A semiconductor device with a memory cell array and terminals that input/output storage data and address data, utilizing internal address lines and switches to distribute address data across two internal lines based on switch information, allowing for uniform loading on external terminals and enabling a larger data width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two 16-bit semiconductor chips are used to form a 32-bit data width device, then the development period is shortened and development cost is lowered, but the loads on external terminals become uneven
Solution Approach 1:
The patent divides the 32-bit data bus into two separate 16-bit data buses (first data bus and second data bus), each handled by a separate semiconductor chip. This segmentation allows each chip to operate independently with balanced terminal loads while collectively providing 32-bit data width functionality.
Solution Approach 2:
The patent combines two 16-bit semiconductor chips to form a single 32-bit data width device. The chips are merged through shared address terminals and coordinated control signals, achieving the functionality of a 32-bit device while maintaining the advantages of using smaller, existing 16-bit chip designs.
2Quantity of substance
If a semiconductor memory device with 32-bit data width is designed from scratch, then the data width requirement is met, but the development period becomes long and development cost increases
Solution Approach 1:
The patent makes existing 16-bit semiconductor chips perform multiple functions by configuring them to work in pairs. Each chip can handle 16 bits of data independently, and when combined, they provide 32-bit data width functionality without requiring new chip designs, thus reducing development time and cost.
Solution Approach 2:
Instead of designing a new 32-bit chip architecture, the patent uses copies of existing 16-bit chip designs. By replicating the proven 16-bit chip architecture twice and coordinating their operation, the system achieves 32-bit data width while avoiding the lengthy development process of creating a new 32-bit design from scratch.
Data Source
AI summary
A semiconductor device and a method of controlling the semiconductor device, the semiconductor device including: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal including: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is included of the entire remaining portion of the address data not including the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address data to the other one of the first internal address line or the second internal address line, when the address data is input to the terminal.