Memory Address Fault Detection via Parity Bits
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Solution Overview
Problem
Existing memory devices often fail to detect errors or faults in the address path, leading to unintended or undesirable errors due to writing or reading data from incorrect locations.
Innovation Solution
A memory device configured to detect errors or faults in the address path by utilizing an error control code to generate parity bits based on both the address and user data, allowing for the identification of errors during write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory devices are used without address fault detection, then device complexity is low, but reliability is poor due to undetected address path errors
Solution Approach 1:
The patent applies preliminary action by generating parity bits for the address path before the actual memory access operation. The address parity is calculated and stored in advance, then compared with newly generated parity bits during read/write operations to detect address faults before they cause incorrect data access.
Solution Approach 2:
The patent uses parity bits as an intermediary mechanism to detect address path errors. Instead of directly monitoring address bus signals, the system encodes address information into parity bits, stores them alongside data, and uses these intermediary parity bits to indirectly detect address faults during data access operations.
2Reliability
If address fault detection is implemented, then reliability improves, but manufacturing precision requirements increase due to additional circuit components
Solution Approach 1:
The patent segments the error detection function into separate components: address parity generation, data parity generation, and parity comparison. This segmentation allows each component to be independently implemented and tested, reducing overall manufacturing complexity while maintaining detection reliability.
3Measurement precision
If parity bits are generated and stored for each memory operation, then measurement precision of address errors improves, but loss of time increases due to additional processing steps
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing address parity bits with the data during the write operation. This eliminates the need for time-consuming parity calculation during read operations, as the pre-stored parity bits are immediately available for comparison, thus reducing access time while maintaining detection accuracy.
Data Source
AI summary
Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.