Memory Address Pattern Generator for Burst Transmission Control
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Solution Overview
Problem
Existing memory test apparatuses face challenges in controlling bit inversion operations, particularly in burst transmission scenarios where inverting lower bits of column addresses can prevent correct access to memory cells.
Innovation Solution
A pattern generator with an address signal generating circuit, operation inhibition signal generating unit, selector, and address signal operation circuit that allows selective bit inversion based on predefined patterns, enabling only desired bits to be inverted at specific times, and accommodating burst length variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an address inverting circuit inverts all bits of the address generated according to the pattern program, then the position of the memory cell to be accessed can be changed in a simple manner, but the lower several bits of column address cannot be inverted during burst transmission, causing incorrect memory access
Solution Approach 1:
The address signal is divided into multiple bit groups, with each bit group corresponding to a specific memory address bit. The operation inhibition signal generating unit generates inhibition signals for each bit group independently, allowing selective inhibition of inversion operations on specific bit groups (such as lower column address bits) while permitting inversion on other bit groups (such as higher row address bits). This segmentation resolves the contradiction by enabling partial inversion rather than all-or-nothing inversion.
Solution Approach 2:
Different inhibition characteristics are applied to different bit groups of the address signal. The operation inhibition signal generating unit creates distinct inhibition patterns where certain bit groups can be inverted while others cannot, depending on the memory operation type. This local differentiation allows the system to maintain reliability for column address bits during burst transmission while preserving the ability to invert row address bits for accessing different memory banks.
2Reliability
If multiple patterns of operation inhibition signals are prepared to control selective bit inversion, then correct memory access can be ensured during burst transmission, but the device complexity increases
Solution Approach 1:
Multiple patterns of operation inhibition signals are prepared in advance and stored in the operation inhibition signal generating unit. These pre-prepared inhibition patterns correspond to different memory operation types (such as burst transmission versus normal access). When a memory operation is initiated, the appropriate pre-computed inhibition pattern is selected and applied, eliminating the need for complex real-time computation of which bits to inhibit. This preliminary preparation reduces the computational complexity during actual memory operations.
Solution Approach 2:
The operation inhibition signal generating unit acts as an intermediary between the address signal generating circuit and the address signal operation circuit. It receives the generated address signal and the operation type information, then produces the appropriate inhibition pattern that mediates the inversion operation. This intermediary layer simplifies the control logic by centralizing the inhibition signal generation and selection, rather than requiring complex control logic distributed throughout the address generation and inversion circuits.
3Device complexity
If all bits of the address signal are inverted regardless of burst transmission mode, then the address signal operation circuit remains simple, but the lower column address bits cannot be correctly accessed during burst operations
Solution Approach 1:
The inhibition pattern applied to the address signal is made dynamic rather than static. The operation inhibition signal generating unit dynamically selects and applies different inhibition patterns based on the current memory operation type. During normal access operations, no inhibition is applied (or full inversion is permitted), while during burst transmission operations, specific inhibition patterns are dynamically applied to protect column address bits. This dynamic adaptation allows the address signal operation circuit to maintain relative simplicity while achieving precise control over which bits are inverted at any given time.
Data Source
AI summary
An address signal generating circuit generates an address signal which designates the address in memory to be accessed. An inversion inhibition signal generating unit generates multiple patterns of inversion inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being inverted. A selector selects one of the multiple patterns of inversion inhibition signals generated by the inversion inhibition signal generating unit, and outputs the inversion inhibition signal thus selected. When an inversion control signal is asserted, an address signal inverting circuit inverts only the bits of the address signal which are not prevented from being inverted according to the inversion inhibition signal selected by the selector, and outputs the resulting address signal.