Memory Address Permutation for Stuck-At Fault Detection
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Solution Overview
Problem
Existing memory control circuits face difficulties in detecting address signal faults, particularly when a stuck-at fault occurs in the address signal lines, as the data and ECC data are written at a specified address, making it challenging to detect errors when read from a different address.
Innovation Solution
The proposed solution involves an I/F conversion circuit that generates an ECC from the data and writes it at a separate address, allowing for the detection of faults in the address signal system by comparing the read ECC with the generated ECC, and using address permutation techniques such as inversion or rotation to ensure accurate fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data and ECC data are written at the same specified address in the memory, then the memory access control is simplified, but it becomes difficult to detect address signal faults
Solution Approach 1:
The patent segments the address space by dividing it into a data area and an ECC data area. The address signal is split into a data address signal and an ECC data address signal, allowing independent control and detection of faults in each segment. This segmentation enables fault detection while maintaining simplified access control within each segment.
Solution Approach 2:
The patent introduces an address conversion circuit as an intermediary between the address signal input and the memory. This circuit converts the input address into separate data addresses and ECC data addresses, enabling fault detection through address comparison while maintaining the simplified single-address input interface.
2Reliability
If separate addresses are used for data and ECC data, then address signal faults can be detected, but the device complexity increases
Solution Approach 1:
The patent merges the fault detection function with the existing address conversion functionality. The address conversion circuit simultaneously performs address translation and fault detection by comparing the original address with the converted ECC data address, eliminating the need for separate detection circuits and reducing overall device complexity.
Solution Approach 2:
The address conversion circuit is designed to perform multiple functions: it converts the input address to separate data and ECC data addresses for memory access, and simultaneously detects address signal faults by comparing addresses. This multi-functionality reduces the need for additional dedicated fault detection hardware.
Data Source
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AI summary
The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.