Memory Address Extension for Host-Controlled PIM Processing
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Solution Overview
Problem
Semiconductor memory devices experience bottlenecks in processing large amounts of data due to the transmission and reception of data between the memory and processor, which can be addressed by integrating processing-in-memory (PIM) capabilities.
Innovation Solution
A host processor generates memory requests and addresses that are mapped to different memory modes, using unused bits in the physical address to distinguish between normal memory and PIM operations, allowing the memory controller to execute commands accordingly, and the memory to perform either normal or PIM operations based on the mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted and received between semiconductor memory device and processor, then processing operations can be performed, but processing speed is limited due to data transmission bottleneck
Solution Approach 1:
The patent combines the processor and memory device into a single integrated unit, merging the functions of data storage and data processing. The processing unit is directly integrated within the memory device, allowing processing operations to be performed on data while it resides in memory, thereby eliminating the need for repeated data transmission between separate memory and processor components.
Solution Approach 2:
The patent introduces a mode selector circuit as an intermediary component that receives mode selection signals from the processor and converts them into appropriate command signals for the processing unit. This intermediary enables seamless communication and coordination between the processor and the integrated processing functionality, facilitating efficient operation without external data transmission.
2Loss of energy
If processing in memory (PIM) capabilities are integrated, then data transmission is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory device into distinct functional units: a memory cell array for data storage, a processing unit for data processing, and a mode selector circuit for control. This segmentation allows each component to perform its specific function efficiently while maintaining clear boundaries that simplify the overall system architecture and control logic.
Solution Approach 2:
The memory device is designed with multi-functionality, capable of operating in different modes (normal memory mode and PIM mode) based on the mode selection signal. The same memory cell array serves both as storage in normal mode and as input data source for processing in PIM mode, eliminating the need for separate dedicated processing memory and reducing overall device complexity.
3Adaptability or versatility
If mode selection signals are used to control processing mode, then operational flexibility is improved, but control complexity increases
Solution Approach 1:
The patent extracts the mode selection functionality into a separate mode selector circuit that is distinct from the processing unit and memory cell array. This extracted control component receives mode selection signals from the external processor and independently generates the appropriate command signals, simplifying the control logic within the processing unit and memory controller while maintaining operational flexibility.
Data Source
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AI summary
Disclosed are a device and method with memory request processing using an extension of a memory address space. An electronic device includes a host processor configured to generate a memory request and a memory address that is mapped to a target memory mode that is any one of available memory modes and is mapped to a physical memory address to which the memory request is to be applied, a memory controller configured to generate the physical memory address and a command according to the target memory mode mapped to the memory address based on the memory request and the memory address received from the host processor, and a memory configured to execute, at the physical memory address, the command received from the memory controller.