Memory Address Protection System for Multi-Processor Coherency
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Solution Overview
Problem
The increasing number of processing cores and threads in computer systems leads to communication bottlenecks due to high latencies and software overheads, as most systems rely on message passing rather than shared memory, making it difficult to effectively apply parallelism to applications.
Innovation Solution
A memory device with an address protection system that allows efficient, low-latency access by multiple processors by creating protected memory locations, ensuring data coherency and reducing software overhead through protected references and a simplified memory controller design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing cores and threads is increased to enhance parallel processing performance, then system performance is improved, but communication latency and software overhead increase disproportionately
Solution Approach 1:
The patent merges message passing and shared memory access into a unified memory interface. Multiple processors access a common memory space through a shared bus, eliminating the need for separate message passing protocols. This combining of access methods reduces communication latency while maintaining support for multiple processing cores and threads.
Solution Approach 2:
The memory device is designed to serve multiple functions: it acts as both shared memory for data storage and communication medium for inter-processor communication. The same memory infrastructure supports both traditional memory access patterns and message passing operations, reducing hardware complexity and software overhead while enabling efficient parallel processing.
2Device complexity
If message passing is used to communicate between processors, then system architecture is simplified, but communication latency and software overhead increase
Solution Approach 1:
The patent combines message passing and shared memory access into a unified memory interface. Multiple processors access a common memory space through a shared bus, eliminating the need for separate message passing protocols. This combining of access methods reduces communication latency while maintaining support for multiple processing cores and threads.
3Reliability
If protected memory locations are implemented to ensure data coherency, then data coherency is improved, but device complexity increases
Solution Approach 1:
The memory controller pre-establishes protection statuses for memory locations before access occurs. When a processor needs to access protected memory, the controller has already configured the appropriate access permissions and coherency protocols. This preliminary setup eliminates the need for complex runtime coherency management, reducing operational complexity while maintaining strong data coherency guarantees.
Data Source
AI summary
A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The protection system is used to prevent at least some of a plurality of processors in a system from accessing addresses designated by one of the processors as a protected memory address. Until the processor releases the protection, only the designating processor can access the memory device at the protected address. If the memory device contains a cache memory, the protection system can alternatively or additionally be used to protect cache memory addresses.