Nonvolatile Memory Address Recovery for Faster Host Reads

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Solution Overview

Problem

The increasing size of data stored in storage devices and the need for improved operating speed in host devices, such as computers and smartphones, are not adequately addressed by existing storage technologies, particularly in nonvolatile memory devices.

Innovation Solution

A storage device with a nonvolatile memory device and a controller that includes error correction and encryption modules to manage physical and logical addresses, utilizing a host performance booster (HPB) to accelerate data transfer by pre-loading physical addresses to the host device, and handling errors through multiple layers of error correction and decryption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional address translation methods are used in nonvolatile memory devices, then device complexity is reduced, but operating speed and data transfer efficiency deteriorate

Engineering Contradiction:
Improveoperating speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The controller pre-loads physical addresses into a buffer memory before the host device needs them. When the host device sends a read command with a logical address, the corresponding physical address is already available in the buffer, eliminating the need for real-time address translation and significantly improving data access speed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A buffer memory is introduced as an intermediary component between the nonvolatile memory and the host device. This buffer temporarily stores pre-loaded physical addresses, acting as a mediator that decouples the address translation process from the data transfer process, thereby improving overall system speed without substantially increasing complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If error correction decoding is performed on physical address entries, then data reliability is improved, but processing time increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Error correction decoding is performed on physical address entries in advance, during the pre-loading phase, rather than waiting until the host device requests data. This preliminary error correction ensures that addresses stored in the buffer are already validated, reducing processing time during actual data operations while maintaining high reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Redundant error correction codes are added to physical address entries before they are pre-loaded into the buffer. This beforehand cushioning provides a safety margin that allows the system to correct errors during the pre-loading phase without impacting the speed of subsequent data retrieval operations

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If host performance booster is implemented to pre-load physical addresses, then data transfer speed is improved, but memory bandwidth consumption increases

Engineering Contradiction:
Improvedata transfer speedVSAvoidmemory bandwidth consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

Instead of pre-loading all physical addresses into the buffer, the system selectively pre-loads only those addresses that are likely to be accessed soon based on the host device's access patterns. This local quality approach optimizes memory bandwidth usage by focusing pre-loading efforts on the most relevant data, thereby improving data transfer speed without excessive bandwidth consumption

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12468452B2Storage device including nonvolatile memory device and controller
Publication Date: 2025.11.11 SAMSUNG ELECTRONICS CO LTD
  • US12468452B2 patent drawing
  • US12468452B2 patent drawing
  • US12468452B2 patent drawing

AI summary

There is provided a storage device which includes a nonvolatile memory device that includes a first area and a second area, and a controller that receives a first command from an external host device, generates a physical address by performing first error correction decoding on a physical address entry included in the first command, reads first data from the second area of the nonvolatile memory device by using the physical address, and outputs the first data to the external host device. When the first error correction decoding fails, the controller reads first map data from the first area from the nonvolatile memory device, translates a logical address included in the first command into the physical address by using the first map data, reads the first data from the second area of the nonvolatile memory device by using the physical address, and outputs the first data to the external host device.